Displaying 7 results from an estimated 7 matches for "_z3addii".
2004 Jun 09
2
[LLVMdev] BranchInst problem
...non-optimal.
Ehm.... I get this:
llc: LiveIntervals.cpp:166: virtual bool
llvm::LiveIntervals::runOnMachineFunction(llvm::MachineFunction&): Assertion
`r2iit != r2iMap_.end()' failed.
- Volodya
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Code after instruction selection
# Machine code for _Z3addii():
<fi #-2> is 4 bytes fixed at location [SP-20]
<fi #-1> is 4 bytes fixed at location [SP-16]
entry (0x8681458):
%reg1024 = load <fi#-1>
%reg1025 = load <fi#-2>
setcc %reg1024, %reg1025
goto %disp(label then)
goto %disp(label else)
then (0x8681688):
%reg1026 = +...
2011 Nov 03
5
[LLVMdev] LLVM problem, please do not ignore
...e my Bachelor thesis.
I am trying to write an llvm pass that just removes all "Add" commands and
gives some statstics.
Nevertheless, I get this segmentation fault:
................some rows about functions, that are not changed by my pass.
The errors occurs after it has modified a "@_Z3addii" function.
store i32 %b.0, i32* %4 and the type is ddddbbm 28
%5 = load i32* %a_addr, align 4 and the type is ddddbbm 27
%6 = load i32* %b_addr, align 4 and the type is ddddbbm 27
%7 = add nsw i32 %5, %6 and the type is ddddbbm 8
store i32 %7, i32* %0, align 4 and the type is dddd...
2004 Jun 09
0
[LLVMdev] BranchInst problem
On Wed, 9 Jun 2004, Vladimir Prus wrote:
> > I assume that the two unconditional gotos are just test code, right? If
> > not, the second one is dead.
>
> Yes, in the final form there will be "iflt" instruction before the first goto,
> making it conditional.
Ah, ok :)
> > > The code after "goto" is disturbing. It looks like spill code, but
2004 Jun 09
2
[LLVMdev] BranchInst problem
Chris Lattner wrote:
> On Tue, 8 Jun 2004, Vladimir Prus wrote:
> > While adding support for branch instructions in my backend, I run into a
> > trouble. The code to handle branches looks like:
> > The machine code after instruction selection is:
> >
> > entry (0x8681458):
> > %reg1024 = load <fi#-1>
> > %reg1025 = load
2004 Jun 09
0
[LLVMdev] BranchInst problem
On Wed, 9 Jun 2004, Vladimir Prus wrote:
> Chris Lattner wrote:
> > > Thanks, this works! I don't yet understand why spill code is needed there
> > > at all, but I'll return to that when I have branches working correctly.
> >
> > I'm not sure either. Can you send the code before and after register
> > allocation?
>
> Attached.
Okay, yeah
2004 Jun 09
2
[LLVMdev] BranchInst problem
...d and rebuild. The bug is still there and the output you've asked
for is attached.
HTH,
Volodya
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Instruction: %tmp.9 = shl int %tmp.8, ubyte 1 ; <int> [#uses=1]
Machine Function
********** REWRITING TWO-ADDR INSTRS **********
********** Function: _Z3addii
********** COMPUTING LIVE INTERVALS **********
********** Function: _Z3addii
entry:
0 %reg1024 = load <fi#-1>
register: %reg1024 +[20,22) +[32,34) +[2,20)
4 %reg1025 = load <fi#-2>
register: %reg1025 +[20,22) +[32,34) +[6,20)
8 setcc %reg1024, %reg1025
12 goto %disp(label then)
16 g...
2011 Nov 03
0
[LLVMdev] LLVM problem, please do not ignore
...sertions
enabled. I recommend compiling with
gmake ENABLE_OPTIMIZED=0 DISABLE_ASSERTIONS=1
if you're going to be developing an LLVM pass.
-- John T.
>
> ................some rows about functions, that are not changed by my
> pass. The errors occurs after it has modified a "@_Z3addii" function.
> store i32 %b.0, i32* %4 and the type is ddddbbm 28
> %5 = load i32* %a_addr, align 4 and the type is ddddbbm 27
> %6 = load i32* %b_addr, align 4 and the type is ddddbbm 27
> %7 = add nsw i32 %5, %6 and the type is ddddbbm 8
> store i32 %7, i32* %0, alig...