llvm dev - Jan 2004 - [LLVMdev] Basic Blocks: Bytecode -> Native Code

Using llc, is it possible to guarantee a 1 to 1 mapping of basic blocks
from LLVM bytecode to native machine code (either in sparc or x86) after
compilation? Optimizations during the compilation are of no concern to
me, I simply require this 1 to 1 mapping.

Thanks.

-- 
jeg
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-----Original Message-----
From: Vikram S. Adve [mailto:vadve at cs.uiuc.edu]
Sent: Sunday, January 25, 2004 7:16 AM
To: Joseph E. Grzywacz
Subject: RE: [LLVMdev] Basic Blocks: Bytecode -> Native Code


[Joseph, I'm sending this again because I didn't copy the list the first
time.]

Yes, this is true for the Sparc back-end.  In fact, it is a fundamental
assumption that is relied on by the runtime tracing framework for dynamic
optimization (not part of 1.1 yet).  I believe it is also true for x86 but I
am not sure.

There is one small violation of that rule, but it should not matter in
practice.  An LLVM conditional branch directly specifies both the true and
the false branch target.  Since that isn't possible with machine code, the
machine code sequence for Sparc (for an LLVM BB ending in a conditional
branch) becomes:

	<code for bb>
	conditional branch to label 1
	nop    ;; delay slot
	unconditional branch to label 2   ;; may be eliminated if fall-through
	nop    ;; delay slot

Technically this is 2 basic blocks, but it is not difficult to recognize and
treat as as special case (and safe).

--Vikram
http://www.cs.uiuc.edu/~vadve
http://llvm.cs.uiuc.edu/

> -----Original Message-----
> From: llvmdev-admin at cs.uiuc.edu [mailto:llvmdev-admin at cs.uiuc.edu]On
> Behalf Of Joseph E. Grzywacz
> Sent: Saturday, January 24, 2004 9:12 PM
> To: llvmdev at cs.uiuc.edu
> Subject: [LLVMdev] Basic Blocks: Bytecode -> Native Code
>
>
> Using llc, is it possible to guarantee a 1 to 1 mapping of basic blocks
> from LLVM bytecode to native machine code (either in sparc or x86) after
> compilation? Optimizations during the compilation are of no concern to
> me, I simply require this 1 to 1 mapping.
>
> Thanks.
>
> --
> jeg
>

> Yes, this is true for the Sparc back-end.  In fact, it is a fundamental
> assumption that is relied on by the runtime tracing framework for dynamic
> optimization (not part of 1.1 yet).  I believe it is also true for x86 but
I
> am not sure.
This is also true for the X86 backend, at least as much as the sparc:
> 	<code for bb>
> 	conditional branch to label 1
> 	nop    ;; delay slot
> 	unconditional branch to label 2   ;; may be eliminated if fall-through
> 	nop    ;; delay slot
>
> Technically this is 2 basic blocks, but it is not difficult to recognize
and
> treat as as special case (and safe).
The exact same thing can happen on X86 as well, if neither destination of
the conditional branch is a fall-through.

Note that in the not-too-distant future, I plan to relax this constraint
in the X86 backend.  In particular, there will be a one-to-several mapping
from LLVM basic blocks to machine basic blocks.  This is required for
adding more efficient switch statement support, and for implementing some
operations on the X86 (e.g. 64-bit shifts: the current implementation uses
conditional moves to work around this, but obviously that won't work on
systems without cmovs :)

In the meantime, there is a 1-1 mapping, but if you can design your stuff
to be easily extensible in the future, it might make forward porting it
easier.

-Chris

-- 
http://llvm.cs.uiuc.edu/
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