CentOS - May 2015 - [CentOS-announce] CentOS-7 disk images for AArch64 Platforms

On Thu, 2015-05-14 at 14:25 -0500, Jim Perrin wrote:
> We've produced a disk image intended to help hardware vendors and
> enthusiasts who are interested in bringing CentOS to their AArch64 based
> platform. This allows a vendor to bypass the installer or to edit the
> disk image before booting in order to test kernel modules or options. It
> is intended for development purposes only, and will only continue
> through the alpha and beta test phases.
Does this mean it may be possible to run basic version of C5, C6 and C7
on Arm64* CPU systems ?  Presumably this will include the Raspberry Pi ?



* Acorn Research machines; manufacturers of the BBC Models A, B, B+,
Master 128 etc - those were the days.


-- 
Regards,

Paul.
England, EU.      Je suis Charlie.

On 05/14/2015 03:51 PM, John R Pierce wrote:
> On 5/14/2015 1:39 PM, Always Learning wrote:
>> Does this mean it may be possible to run basic version of C5, C6 and C7
>> on Arm64* CPU systems ?  Presumably this will include the Raspberry Pi
?
> 
> is the rasberry pi ARMv8 (arm64) ?  I thought it was v7 (32bit only)
> 
You are correct, the Pi is not armv8.

This is for larger devices ... although, there are now a some armv8
embedded devices too.

We SHOULD also have an armv7hl branch at some point too (we have just
really started working on that) ... and I think that will run on the
raspberry pi2 when done (though not the original).

We are trying for large data center devices not cell phones :)

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On Thu, 2015-05-14 at 13:51 -0700, John R Pierce wrote:
> On 5/14/2015 1:39 PM, Always Learning wrote:
> > Does this mean it may be possible to run basic version of C5, C6 and
C7
> > on Arm64* CPU systems ?  Presumably this will include the Raspberry Pi
?
> is the rasberry pi ARMv8 (arm64) ?  I thought it was v7 (32bit only)
~~~~~~~~~~

Raspberry Pi 2 Model B is the second generation Raspberry Pi.
A 900MHz quad-core ARM Cortex-A7 CPU
128-bit AMBA? 4 AXI bus interface. 

The Cortex-A7 processor builds on the energy-efficient 8-stage pipeline
of the Cortex-A5 processor. .... with 64-bit load-store path, 128-bit
AMBA 4 AXI buses and increased TLB size (256 entry, up from 128
entry ....

ARMv7-A

The MPE extends the Cortex-A7 processor's FPU to provide a quad-MAC and
additional 64-bit and 128-bit register set supporting a rich set of SIMD
operations over 8, 16 and 32-bit integer and 32-bit Floating-Point data
quantities.

~~~~~~~~~~

Except for the above, can't find any specific mentioned of 32 or 64 bit
CPU.


-- 
Regards,

Paul.
England, EU.      Je suis Charlie.