Nouveau - Sep 2024 - [PATCH v3 0/2] drm/nouveau: Add drm_panic support for nv50+

This series adds basic drm_panic support for nouveau.
Patches 1 Add ABGR2101010 support in drm_panic.
Patch 2 registers nouveau to drm_panic, and handle tiling.
I've tested on a GTX1650 (Turing) and GF 8800 GT (Tesla), while
running Gnome/Wayland desktop, and in VT.

It should work on other nv50+ cards, but I didn't test them.

To test it, you need to build your kernel with CONFIG_DRM_PANIC=y, and run:

echo c > /proc/sysrq-trigger

or you can enable CONFIG_DRM_PANIC_DEBUG and run:

echo 1 > /sys/kernel/debug/dri/0/drm_panic_plane_0

v2:
 * Rebase and drop already merged patches.
 * Rework the tiling algorithm, using "swizzle" to compute the offset
   inside the block.
   
v3:
 * Fix support for Tesla GPU, which have simpler tiling.
 * Drop "add a private pointer to struct drm_scanout_buffer".
 * Use nouveau_framebuffer_get_layout() to get the tiling parameters.
 * Have 2 set_pixel() functions, depending on GPU family.
 
Jocelyn Falempe (2):
  drm/panic: Add ABGR2101010 support
  drm/nouveau: Add drm_panic support for nv50+

 drivers/gpu/drm/drm_panic.c             |  10 ++
 drivers/gpu/drm/nouveau/dispnv50/wndw.c | 139 +++++++++++++++++++++++-
 2 files changed, 147 insertions(+), 2 deletions(-)


base-commit: 9d443deb0441b9dbb22a9aac3b471da05220df1b
-- 
2.46.0

Add support for ABGR2101010, used by the nouveau driver.

Signed-off-by: Jocelyn Falempe <jfalempe at redhat.com>
---
 drivers/gpu/drm/drm_panic.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/drm_panic.c b/drivers/gpu/drm/drm_panic.c
index 74412b7bf936..0a9ecc1380d2 100644
--- a/drivers/gpu/drm/drm_panic.c
+++ b/drivers/gpu/drm/drm_panic.c
@@ -209,6 +209,14 @@ static u32 convert_xrgb8888_to_argb2101010(u32 pix)
 	return GENMASK(31, 30) /* set alpha bits */ | pix | ((pix >> 8) &
0x00300C03);
 }
 
+static u32 convert_xrgb8888_to_abgr2101010(u32 pix)
+{
+	pix = ((pix & 0x00FF0000) >> 14) |
+	      ((pix & 0x0000FF00) << 4) |
+	      ((pix & 0x000000FF) << 22);
+	return GENMASK(31, 30) /* set alpha bits */ | pix | ((pix >> 8) &
0x00300C03);
+}
+
 /*
  * convert_from_xrgb8888 - convert one pixel from xrgb8888 to the desired
format
  * @color: input color, in xrgb8888 format
@@ -242,6 +250,8 @@ static u32 convert_from_xrgb8888(u32 color, u32 format)
 		return convert_xrgb8888_to_xrgb2101010(color);
 	case DRM_FORMAT_ARGB2101010:
 		return convert_xrgb8888_to_argb2101010(color);
+	case DRM_FORMAT_ABGR2101010:
+		return convert_xrgb8888_to_abgr2101010(color);
 	default:
 		WARN_ONCE(1, "Can't convert to %p4cc\n", &format);
 		return 0;
-- 
2.46.0

Add drm_panic support, for nv50+ cards.
It's enough to get the panic screen while running Gnome/Wayland on a
GTX 1650.
It doesn't support multi-plane or compressed format.
Support for other formats and older cards will come later.
Tiling is only tested on GTX1650, and might be wrong for other cards.

Signed-off-by: Jocelyn Falempe <jfalempe at redhat.com>
---

v2:
 * Rebase and drop already merged patches.
 * Rework the tiling algorithm, using "swizzle" to compute the offset
   inside the block.
   
v3:
 * Fix support for Tesla GPU, which have simpler tiling.
 * Use nouveau_framebuffer_get_layout() to get the tiling parameters.
 * Have 2 set_pixel() functions, depending on GPU family.

 drivers/gpu/drm/nouveau/dispnv50/wndw.c | 139 +++++++++++++++++++++++-
 1 file changed, 137 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c
b/drivers/gpu/drm/nouveau/dispnv50/wndw.c
index 7a2cceaee6e9..419c5f359711 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c
@@ -30,11 +30,16 @@
 #include <nvhw/class/cl507e.h>
 #include <nvhw/class/clc37e.h>
 
+#include <linux/iosys-map.h>
+
 #include <drm/drm_atomic.h>
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_blend.h>
-#include <drm/drm_gem_atomic_helper.h>
 #include <drm/drm_fourcc.h>
+#include <drm/drm_framebuffer.h>
+#include <drm/drm_gem_atomic_helper.h>
+#include <drm/drm_panic.h>
+#include <drm/ttm/ttm_bo.h>
 
 #include "nouveau_bo.h"
 #include "nouveau_gem.h"
@@ -577,6 +582,125 @@ nv50_wndw_prepare_fb(struct drm_plane *plane, struct
drm_plane_state *state)
 	return 0;
 }
 
+#define NV_TILE_BLK_BASE_HEIGHT_TESLA 4 /* In pixel */
+#define NV_TILE_BLK_BASE_HEIGHT 8	/* In pixel */
+#define NV_TILE_GOB_SIZE 64	/* In bytes */
+#define NV_TILE_BLK_WIDTH (NV_TILE_GOB_SIZE / 4) /* For 32 bits pixel */
+
+/* Only used by drm_panic get_scanout_buffer() and set_pixel(), so it is
+ * protected by the drm panic spinlock
+ */
+static u32 nv50_panic_blk_h;
+
+/* Return the framebuffer offset of the start of the block where pixel(x,y) is
*/
+static u32
+nv50_get_block_off(unsigned int x, unsigned int y, unsigned int width)
+{
+	u32 blk_x, blk_y, blk_columns;
+
+	blk_columns = DIV_ROUND_UP(width, NV_TILE_BLK_WIDTH);
+	blk_x = x / NV_TILE_BLK_WIDTH;
+	blk_y = y / nv50_panic_blk_h;
+
+	return ((blk_y * blk_columns) + blk_x) * NV_TILE_GOB_SIZE * nv50_panic_blk_h;
+}
+
+/* Turing and later have 2 level of tiles inside the block */
+static void
+nv50_set_pixel_swizzle(struct drm_scanout_buffer *sb, unsigned int x,
+		       unsigned int y, u32 color)
+{
+	u32 blk_off, off, swizzle;
+
+	blk_off = nv50_get_block_off(x, y, sb->width);
+
+	y = y % nv50_panic_blk_h;
+
+	/* Inside the block, use the fast address swizzle to compute the offset
+	 * For nvidia blocklinear, bit order is yn..y3 x3 y2 x2 y1 y0 x1 x0
+	 */
+	swizzle = (x & 3) | (y & 3) << 2 | (x & 4) << 2 | (y
& 4) << 3;
+	swizzle |= (x & 8) << 3 | (y >> 3) << 7;
+	off = blk_off + swizzle * 4;
+
+	iosys_map_wr(&sb->map[0], off, u32, color);
+}
+
+static void
+nv50_set_pixel(struct drm_scanout_buffer *sb, unsigned int x, unsigned int y,
+	       u32 color)
+{
+	u32 blk_off, off;
+
+	blk_off = nv50_get_block_off(x, y, sb->width);
+
+	x = x % NV_TILE_BLK_WIDTH;
+	y = y % nv50_panic_blk_h;
+	off = blk_off + (x + y * NV_TILE_BLK_WIDTH) * 4;
+
+	iosys_map_wr(&sb->map[0], off, u32, color);
+}
+
+static u32
+nv50_get_block_height(u32 tile_mode, u16 chipset)
+{
+	if (chipset < 0xc0)
+		return NV_TILE_BLK_BASE_HEIGHT_TESLA * (1 << tile_mode);
+	else
+		return NV_TILE_BLK_BASE_HEIGHT * (1 << (tile_mode >> 4));
+}
+
+static int
+nv50_wndw_get_scanout_buffer(struct drm_plane *plane, struct drm_scanout_buffer
*sb)
+{
+	struct drm_framebuffer *fb;
+	struct nouveau_bo *nvbo;
+	struct nouveau_drm *drm = nouveau_drm(plane->dev);
+	u16 chipset = drm->client.device.info.chipset;
+	u32 tile_mode;
+	u8 kind;
+
+	if (!plane->state || !plane->state->fb)
+		return -EINVAL;
+
+	fb = plane->state->fb;
+	nvbo = nouveau_gem_object(fb->obj[0]);
+
+	/* Don't support compressed format, or multiplane yet. */
+	if (nvbo->comp || fb->format->num_planes != 1)
+		return -EOPNOTSUPP;
+
+	if (nouveau_bo_map(nvbo)) {
+		pr_warn("nouveau bo map failed, panic won't be displayed\n");
+		return -ENOMEM;
+	}
+
+	if (nvbo->kmap.bo_kmap_type & TTM_BO_MAP_IOMEM_MASK)
+		iosys_map_set_vaddr_iomem(&sb->map[0], (void __iomem *)
nvbo->kmap.virtual);
+	else
+		iosys_map_set_vaddr(&sb->map[0], nvbo->kmap.virtual);
+
+	sb->height = fb->height;
+	sb->width = fb->width;
+	sb->pitch[0] = fb->pitches[0];
+	sb->format = fb->format;
+
+	nouveau_framebuffer_get_layout(fb, &tile_mode, &kind);
+	if (kind) {
+		/* If tiling is enabled, use set_pixel() to display correctly.
+		 * Only handle 32bits format for now.
+		 */
+		if (fb->format->cpp[0] != 4)
+			return -EOPNOTSUPP;
+		nv50_panic_blk_h = nv50_get_block_height(tile_mode, chipset);
+		if (chipset >= 0x160)
+			sb->set_pixel = nv50_set_pixel_swizzle;
+		else
+			sb->set_pixel = nv50_set_pixel;
+	}
+	return 0;
+}
+
 static const struct drm_plane_helper_funcs
 nv50_wndw_helper = {
 	.prepare_fb = nv50_wndw_prepare_fb,
@@ -584,6 +708,14 @@ nv50_wndw_helper = {
 	.atomic_check = nv50_wndw_atomic_check,
 };
 
+static const struct drm_plane_helper_funcs
+nv50_wndw_primary_helper = {
+	.prepare_fb = nv50_wndw_prepare_fb,
+	.cleanup_fb = nv50_wndw_cleanup_fb,
+	.atomic_check = nv50_wndw_atomic_check,
+	.get_scanout_buffer = nv50_wndw_get_scanout_buffer,
+};
+
 static void
 nv50_wndw_atomic_destroy_state(struct drm_plane *plane,
 			       struct drm_plane_state *state)
@@ -732,7 +864,10 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, struct
drm_device *dev,
 		return ret;
 	}
 
-	drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);
+	if (type == DRM_PLANE_TYPE_PRIMARY)
+		drm_plane_helper_add(&wndw->plane, &nv50_wndw_primary_helper);
+	else
+		drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);
 
 	if (wndw->func->ilut) {
 		ret = nv50_lut_init(disp, mmu, &wndw->ilut);
-- 
2.46.0

On 13/09/2024 09:03, Jocelyn Falempe wrote:
> This series adds basic drm_panic support for nouveau.
> Patches 1 Add ABGR2101010 support in drm_panic.
> Patch 2 registers nouveau to drm_panic, and handle tiling.
> I've tested on a GTX1650 (Turing) and GF 8800 GT (Tesla), while
> running Gnome/Wayland desktop, and in VT.
I got a test report, that it also works correctly on a GT1030 (Pascal).
So I'm confident it works also on earlier GPUs.

Best regards,

-- 

Jocelyn
> 
> It should work on other nv50+ cards, but I didn't test them.
> 
> To test it, you need to build your kernel with CONFIG_DRM_PANIC=y, and run:
> 
> echo c > /proc/sysrq-trigger
> 
> or you can enable CONFIG_DRM_PANIC_DEBUG and run:
> 
> echo 1 > /sys/kernel/debug/dri/0/drm_panic_plane_0
> 
> v2:
>   * Rebase and drop already merged patches.
>   * Rework the tiling algorithm, using "swizzle" to compute the
offset
>     inside the block.
>     
> v3:
>   * Fix support for Tesla GPU, which have simpler tiling.
>   * Drop "add a private pointer to struct drm_scanout_buffer".
>   * Use nouveau_framebuffer_get_layout() to get the tiling parameters.
>   * Have 2 set_pixel() functions, depending on GPU family.
>   
> Jocelyn Falempe (2):
>    drm/panic: Add ABGR2101010 support
>    drm/nouveau: Add drm_panic support for nv50+
> 
>   drivers/gpu/drm/drm_panic.c             |  10 ++
>   drivers/gpu/drm/nouveau/dispnv50/wndw.c | 139 +++++++++++++++++++++++-
>   2 files changed, 147 insertions(+), 2 deletions(-)
> 
> 
> base-commit: 9d443deb0441b9dbb22a9aac3b471da05220df1b