search for: drm_scanout_buffer

...> /sys/kernel/debug/dri/0/drm_panic_plane_0 v2: * Rebase and drop already merged patches. * Rework the tiling algorithm, using "swizzle" to compute the offset inside the block. Jocelyn Falempe (3): drm/panic: Add ABGR2101010 support drm/panic: add a private pointer to struct drm_scanout_buffer drm/nouveau: Add drm_panic support for nv50+ drivers/gpu/drm/drm_panic.c | 10 +++ drivers/gpu/drm/nouveau/dispnv50/wndw.c | 107 +++++++++++++++++++++++- include/drm/drm_panic.h | 7 ++ 3 files changed, 122 insertions(+), 2 deletions(-) base-commit: e8653e63e83...

...DIV_ROUND_UP(width, NV_TILE_BLK_WIDTH); + blk_x = x / NV_TILE_BLK_WIDTH; + blk_y = y / nv50_panic_blk_h; + + return ((blk_y * blk_columns) + blk_x) * NV_TILE_GOB_SIZE * nv50_panic_blk_h; +} + +/* Turing and later have 2 level of tiles inside the block */ +static void +nv50_set_pixel_swizzle(struct drm_scanout_buffer *sb, unsigned int x, + unsigned int y, u32 color) +{ + u32 blk_off, off, swizzle; + + blk_off = nv50_get_block_off(x, y, sb->width); + + y = y % nv50_panic_blk_h; + + /* Inside the block, use the fast address swizzle to compute the offset + * For nvidia blocklinear, bit order is yn..y3...

...+ blk_x = x / NV_TILE_BLK_WIDTH; > + blk_y = y / nv50_panic_blk_h; > + > + return ((blk_y * blk_columns) + blk_x) * NV_TILE_GOB_SIZE * nv50_panic_blk_h; > +} > + > +/* Turing and later have 2 level of tiles inside the block */ > +static void > +nv50_set_pixel_swizzle(struct drm_scanout_buffer *sb, unsigned int x, > + unsigned int y, u32 color) > +{ > + u32 blk_off, off, swizzle; > + > + blk_off = nv50_get_block_off(x, y, sb->width); > + > + y = y % nv50_panic_blk_h; > + > + /* Inside the block, use the fast address swizzle to compute the offset >...

...ys/kernel/debug/dri/0/drm_panic_plane_0 v2: * Rebase and drop already merged patches. * Rework the tiling algorithm, using "swizzle" to compute the offset inside the block. v3: * Fix support for Tesla GPU, which have simpler tiling. * Drop "add a private pointer to struct drm_scanout_buffer". * Use nouveau_framebuffer_get_layout() to get the tiling parameters. * Have 2 set_pixel() functions, depending on GPU family. Jocelyn Falempe (2): drm/panic: Add ABGR2101010 support drm/nouveau: Add drm_panic support for nv50+ drivers/gpu/drm/drm_panic.c | 10 ++ drive...

...; >> + blk_y = y / nv50_panic_blk_h; >> + >> + return ((blk_y * blk_columns) + blk_x) * NV_TILE_GOB_SIZE * nv50_panic_blk_h; >> +} >> + >> +/* Turing and later have 2 level of tiles inside the block */ >> +static void >> +nv50_set_pixel_swizzle(struct drm_scanout_buffer *sb, unsigned int x, >> + unsigned int y, u32 color) >> +{ >> + u32 blk_off, off, swizzle; >> + >> + blk_off = nv50_get_block_off(x, y, sb->width); >> + >> + y = y % nv50_panic_blk_h; >> + >> + /* Inside the block, use the fast addres...

...ys/kernel/debug/dri/0/drm_panic_plane_0 v2: * Rebase and drop already merged patches. * Rework the tiling algorithm, using "swizzle" to compute the offset inside the block. v3: * Fix support for Tesla GPU, which have simpler tiling. * Drop "add a private pointer to struct drm_scanout_buffer". * Use nouveau_framebuffer_get_layout() to get the tiling parameters. * Have 2 set_pixel() functions, depending on GPU family. v4: * Refactor and move the tiling code from nouveau_display.c to dispnv50/tile.h, so that in can be re-used by drm_panic. (Lyude) * Refactor get_scanout_buffe...

.../linux/workqueue.h, drivers/gpu/drm/nouveau/dispnv50/disp.h, ...): include/linux/list.h:83:21: sparse: sparse: self-comparison always evaluates to true vim +675 drivers/gpu/drm/nouveau/dispnv50/wndw.c 652 653 static int 654 nv50_wndw_get_scanout_buffer(struct drm_plane *plane, struct drm_scanout_buffer *sb) 655 { 656 struct drm_framebuffer *fb; 657 struct nouveau_bo *nvbo; 658 659 if (!plane->state || !plane->state->fb) 660 return -EINVAL; 661 662 fb = plane->state->fb; 663 nvbo = nouveau_gem_object(fb->obj[0]); 664 665 /* Don't su...