llvm dev - Jan 2013 - [LLVMdev] Initial thoughts on an LLVM backend for N-address generic assembly

Hi,

    I have some applications, which have been compiled into llvm IR and 
then linked into executable programs. I have some static information got 
from analysing llvm IR, and some dynamic information, like which binary 
branch is taken, from hardware sampler. I am wondering whether there are 
some ways to map binary code with LLVM IR. The only way I know is to use 
debug info, since both llvm IR and binary code can be mapped to source 
code. I feel this method is not precise. Are there some other methods?

    Best,

    Thanks a lot!

                                                                                
Linhai

Hi Linhai,
> Hi,
>
>     I have some applications, which have been compiled into llvm IR and
then
> linked into executable programs. I have some static information got from
> analysing llvm IR, and some dynamic information, like which binary branch
is
> taken, from hardware sampler. I am wondering whether there are some ways to
map
> binary code with LLVM IR. The only way I know is to use debug info, since
both
> llvm IR and binary code can be mapped to source code. I feel this method is
not
> precise. Are there some other methods?
I think you should use debug info, however you aren't obliged to use debug
info
coming from the original language source code: you could create artificial debug
info from the IR file.  For example for each instruction in the IR file, you
attach debug info to it that says that the "file" is the given IR
file, the
"function" is the function the instruction is in, and the
"line" is the line
within the IR file of the instruction.

Ciao, Duncan.

Hi all,

i'm just starting out with LLVM (although i've been observing its  
evolution since that first release some years ago :)

I would like to develop a backend for a generic assembly-like  
language, called NAC (N-Address Code). More info on NAC can be found  
here:
http://www.nkavvadias.com/hercules/nac-refman.html (HTML)
http://www.nkavvadias.com/hercules/nac-refman.pdf (PDF)

You can consider NAC similar to an LLVM subset for hardware synthesis.  
Although NAC was developed independently, certain decisions taken when  
designing it, may or may not defer from other textual IRs like LLVM or  
PTX.

I have a number of questions:

1) It seems to me that a template backend either the C backend or  
NVPTX are possible starting points. However, only NVPTX makes use of  
tblgen which removes some burder from the backend developer. I also  
think that a tblgen-based backend like NVPTX is easier to maintain in  
the long term. What do you think?

2) NAC uses the following statement form (for any given statement):

dst1, dst2, ..., dstm <= op src1, src2, ..., srcn;

which expresses an operation op with n source operands and m  
destination operands. Do you think that tblgen supports such form or  
should I sanitize it?

3) The NAC memory model uses separate address spaces per array. A  
general-use stack/heap might also be supported. Should I use dot  
directives to declare each address space in use for a given  
translation unit/module?

4) What is the maximum that I can get from tblgen? Which C++ source  
files cannot be generated by .td files and always have to be coded by  
hand?

In the end, source code for the LLVM->NAC backend and a NAC  
interpreter will be released, probably as third-party BSD-licensed  
tools.


Best regards
Nikolaos Kavvadias