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I have a simple script that sends one file to two locations on the same destination server. Here's the code: DEST="remotehost" SRC="/home/boss/application.conf" DST1="/home/user1/application.conf" DST2="/home/user2/application.conf" RSYNC1=`rsync -caW -e ssh $SRC $DEST:$DST1` RSYNC2=`rsync -caW -e ssh $SRC $DEST:$DST2` This runs every 5 minutes. What I'm seeing is the first location occasionally gets a *partial* file, but the second lo...

...rewall| | | ----------- | | | | ------------ ------------ | | | | | DST1 | | DST2 | | | | | ----------- ----------- For example I want make NAT if packet destination is DST1 (network or PC) but not if destination is DST2. Thanks on advance.

...rent implementation? If I have TableGen code like the following... 1242 def SDTTestNode : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>; 1243 def TestNode : SDNode<"NVPTXISD::TestNode", SDTTestNode>; 1244 1245 def MyTestNode : NVPTXInst<(outs Int32Regs:$dst0, Int32Regs:$dst1), 1246 (ins Int32Regs:$a), 1247 "test $dst0, $dst1, $a;", 1248 [(set Int32Regs:$dst0, Int32Regs:$dst1, (TestNode Int32Regs:$a))]>; ... TableGen crashes with the following stack trace: #0 0x00007fff8f372...

...then umount /tmp/rsync_bug/mnt rm -rf /tmp/rsync_bug fi mkdir /tmp/rsync_bug cd /tmp/rsync_bug mkdir mnt mount -t tmpfs tmpfs mnt ln -s BLABLA mnt/test mkdir src ln -s /tmp/rsync_bug/mnt src/dir rsync -aHx --delete --numeric-ids src/ dst1 rm src/dir mkdir src/dir cp -a mnt/test src/dir/ rsync -aHx --delete --numeric-ids --link-dest /tmp/rsync_bug/dst1 src/ dst2 || echo RSYNC FAIL Output for me: buczek at theinternet:~$ sudo ./rsync-bug.sh + '[' -d /tmp/rsync_bug ']' + umount /tm...

...st_src_reg src3 = undef_src); + st_src_reg src3 = undef_src, + unsigned precise = 0); glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, unsigned op, st_dst_reg dst, st_dst_reg dst1, st_src_reg src0 = undef_src, st_src_reg src1 = undef_src, st_src_reg src2 = undef_src, + st_src_reg src3 = undef_src, +...

...I have TableGen code like the following... > > 1242 def SDTTestNode : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>; > 1243 def TestNode : SDNode<"NVPTXISD::TestNode", SDTTestNode>; > 1244 > 1245 def MyTestNode : NVPTXInst<(outs Int32Regs:$dst0, Int32Regs:$dst1), > 1246 (ins Int32Regs:$a), > 1247 "test $dst0, $dst1, $a;", > 1248 [(set Int32Regs:$dst0, Int32Regs:$dst1, > (TestNode Int32Regs:$a))]>; > > ... TableGen crashes with the following stac...

...have TableGen code like the following... > > 1242 def SDTTestNode : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>; > 1243 def TestNode : SDNode<"NVPTXISD::TestNode", SDTTestNode>; > 1244 > 1245 def MyTestNode : NVPTXInst<(outs Int32Regs:$dst0, Int32Regs:$dst1), > 1246 (ins Int32Regs:$a), > 1247 "test $dst0, $dst1, $a;", > 1248 [(set Int32Regs:$dst0, Int32Regs:$dst1, (TestNode Int32Regs:$a))]>; > > ... TableGen crashes with the following stack tr...

...like the following... >> >> 1242 def SDTTestNode : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>; >> 1243 def TestNode : SDNode<"NVPTXISD::TestNode", SDTTestNode>; >> 1244 >> 1245 def MyTestNode : NVPTXInst<(outs Int32Regs:$dst0, Int32Regs:$dst1), >> 1246 (ins Int32Regs:$a), >> 1247 "test $dst0, $dst1, $a;", >> 1248 [(set Int32Regs:$dst0, Int32Regs:$dst1, (TestNode Int32Regs:$a))]>; >> >> ... TableGen crashes with th...

https://bugzilla.samba.org/show_bug.cgi?id=11866 Bug ID: 11866 Summary: rsync fails (failed to re-stat) when using double fuzzy + link-dest on renamed files Product: rsync Version: 3.1.1 Hardware: All OS: Linux Status: NEW Severity: normal Priority: P5 Component:

...; fire in a particular pass. >> >> One feature I think we ought to have that isn't on the requirements >> list already, is that I think we should have a means to support rules >> with more than one match root. For example (using SelectionDAG patterns): >> (set $dst1:GPR32, (i32 (load $ptr:GPR64))) >> (set $dst2:GPR32, (i32 (load (add $ptr:GPR64 4)))) >> into: >> (set $tmp:GPR64, (v2s32 (load $ptr:GPR64))) >> (set $dst1, (extractelt $tmp:GPR64, 0)) >> (set $dst2, (extractelt $tmp:GPR64, 1)) >> Or something along those...

...r rarely fire in a particular pass. >>> >>> One feature I think we ought to have that isn't on the requirements list already, is that I think we should have a means to support rules with more than one match root. For example (using SelectionDAG patterns): >>> (set $dst1:GPR32, (i32 (load $ptr:GPR64))) >>> (set $dst2:GPR32, (i32 (load (add $ptr:GPR64 4)))) >>> into: >>> (set $tmp:GPR64, (v2s32 (load $ptr:GPR64))) >>> (set $dst1, (extractelt $tmp:GPR64, 0)) >>> (set $dst2, (extractelt $tmp:GPR64, 1)) >>>...

...(ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3), >> "if (!$src1) $dst=memd($src2+#$src3)", >> []>; >> >> let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in >> -def POST_LDrid_cPt : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2), >> +def POST_LDrid_cPt : LDInst2PI<(outs DoubleRegs:$dst1, IntRegs:$dst2), >> (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3), >> "if ($src1) $dst1 = memd($src2++#$src3)", >> [], >>...

> On Nov 10, 2017, at 10:19 AM, Hal Finkel via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > On 11/10/2017 11:12 AM, Amara Emerson via llvm-dev wrote: >> Hi everyone, >> >> This RFC concerns the design and architecture of a generic machine instruction combiner/optimizer framework to be developed as part of the GISel pipeline. As we transition from

Running Tomb Raider on Nouveau I found some flicker caused by ignoring precise modifiers on variables inside Nouveau. This series add precise/invariant handling to TGSI, which can be then used by drivers to disable certain unsafe optimisations which may otherwise alter calculations, which depend on having the same result across shaders. This series fixes this bug in Tomb Raider and one CTS test

...e starting points. However, only NVPTX makes use of tblgen which removes some burder from the backend developer. I also think that a tblgen-based backend like NVPTX is easier to maintain in the long term. What do you think? 2) NAC uses the following statement form (for any given statement): dst1, dst2, ..., dstm <= op src1, src2, ..., srcn; which expresses an operation op with n source operands and m destination operands. Do you think that tblgen supports such form or should I sanitize it? 3) The NAC memory model uses separate address spaces per array. A general-use stack/heap m...

...f the sources are the same register then the destinations must be as well. My instructions look like this, however: %V2<def> = COPY %V6 %V6<def> = COPY %V2_LO (isNopCopy is called with src and dest of the first instruction switched.) So dst2 == src1 but src2 is a subregister of dst1. Is there some assumption that size(src) == size(dst)? This second COPY, with size(src) != size(dst) was generated in InstrEmitter::EmitSubregNode at // Create the extract_subreg machine instruction. So it's not out-of-tree code. Am I missing something or should the assert condition be part...

...} } }; + union { + struct in6_addr *in6; + struct in_addr *in; + } remote, local; + unsigned short outer_family = 0, beet = 0; int i; int err; int header_len = 0; @@ -75,7 +80,6 @@ for (i = 0; i < nx; i++) { struct dst_entry *dst1 = dst_alloc(&xfrm4_dst_ops); struct xfrm_dst *xdst; - int tunnel = 0; if (unlikely(dst1 == NULL)) { err = -ENOBUFS; @@ -96,21 +100,45 @@ dst1->next = dst_prev; dst_prev = dst1; - if (xfrm[i]->props.mode) { - rem...

Dear subscribers, I have made a simulation using loops rather than apply, simply because the loop function seems more natural to me. However, the current simulation takes forever and I have decided - finally - to learn how to use apply, but - as many other people before me - I am having a hard time changing habits. My current problem is: My current code for the loop is: distances <-

...for your other questions, I'm no expert, but you might want to take a look at the available tutorials (http://llvm.org/docs/WritingAnLLVMBackend.html and http://jonathan2251.github.com/lbd/). -- Ahmed Bougacha > 2) NAC uses the following statement form (for any given statement): > > dst1, dst2, ..., dstm <= op src1, src2, ..., srcn; > > which expresses an operation op with n source operands and m destination > operands. Do you think that tblgen supports such form or should I sanitize > it? > > 3) The NAC memory model uses separate address spaces per array. A &g...

...+ * NVCopyData420 + * TODO: use DMA instead of CPU copy + * used by NVPutImage() function to copy (image)data from + * system RAM to VRAM and change data order. + * + * @param src1 source buffer (luma ?) + * @param src2 source buffer (chroma1 ?) + * @param src3 source buffer (chroma2 ?) + * @param dst1 destination buffer + * @param srcPitch pitch of src1 + * @param srcPitch2 pitch of src2, src3 + * @param dstPitch pitch of dst1 + * @param h number of lines to copy + * @param w length of lines to copy + */ static void NVCopyData420(unsigned char *src1, unsigned char *src2, unsigned char *sr...