Markus Weinhardt via llvm-dev
2016-May-16 19:56 UTC
[llvm-dev] SDNode type UNDEF in new llvm-backend
Hello!
I'm new to llvm and have the following problem trying to implement a new
backend, based on the LEG-backend by Fraser Cormack.
I used the standard clang command (under Ubuntu) to generate main.bc
from the following tiny program:
main.c:
void main() {
volatile int a, b, c;
c = a - b;
}
I then used the following command:
llc -march=lacore -debug -print-after-all main.bc -o main.s
The program terminated with an assertion violation, see output below.
The UNDEF node (t3) apparently causes the problem. But, according to my
understanding, this node is already generated in the IR->DAG translation
and already exisiting in the initial selection DAG (in the load and
store commands). Therefore, it is probably not related to my own,
error-prone target implementation. That makes the problem even harder to
understand. I could not find out where the UNDEF SDNode is generated.
Thank you in advance for any hints!
Best regards,
Markus
---------------------------------------------------------------------
...
*** IR Dump After Module Verifier ***
; Function Attrs: nounwind uwtable
define void @main() #0 {
%a = alloca i32, align 4
%b = alloca i32, align 4
%c = alloca i32, align 4
%1 = load volatile i32, i32* %a, align 4
%2 = load volatile i32, i32* %b, align 4
%3 = sub nsw i32 %1, %2
store volatile i32 %3, i32* %c, align 4
ret void
}
---- Branch Probability Info : main ----
Computing probabilities for
=== main
Initial selection DAG: BB#0 'main:'
SelectionDAG has 11 nodes:
t2: i32 = Constant<0>
t0: ch = EntryToken
t4: i32,ch = load<Volatile LD4[%a]> t0, FrameIndex:i32<0>,
undef:i32
t6: i32,ch = load<Volatile LD4[%b]> t4:1, FrameIndex:i32<1>,
undef:i32
t7: i32 = sub t4, t6
t9: ch = store<Volatile ST4[%c]> t6:1, t7, FrameIndex:i32<2>,
undef:i32
t10: ch = RetFlag t9
...
*** Final schedule ***
SU(2): t3: i32 = undef
SU(4): t4: i32,ch = load<Volatile LD4[%a]> t0, FrameIndex:i32<0>,
undef:i32
SU(5): t6: i32,ch = load<Volatile LD4[%b]> t4:1, FrameIndex:i32<1>,
undef:i32
SU(3): t7: i32 = sub t4, t6
SU(1): t9: ch = store<Volatile ST4[%c]> t6:1, t7, FrameIndex:i32<2>,
undef:i32
SU(0): t10: ch = RetFlag t9
t3: i32 = undef
This target-independent node should have been selected!
UNREACHABLE executed at
/home/markus/llvm_inst/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp:889!
--
Prof. Dr.-Ing. Markus Weinhardt - Hochschule Osnabrück
Visiting Researcher at www.inesc-id.pt -ESDA, Lisbon/PT
mweinhardt at computer.org - Tel.nr. +49-(0)541-969 3445
Postf. 1940, 49009 Osnabrück (Artilleriestr. 46, SB223)
http://www.ecs.hs-osnabrueck.de/weinhardt.html
Mehdi Amini via llvm-dev
2016-May-17 05:36 UTC
[llvm-dev] SDNode type UNDEF in new llvm-backend
> On May 16, 2016, at 12:56 PM, Markus Weinhardt via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hello! > > I'm new to llvm and have the following problem trying to implement a new > backend, based on the LEG-backend by Fraser Cormack. > > I used the standard clang command (under Ubuntu) to generate main.bc > from the following tiny program: > > main.c: > void main() { > volatile int a, b, c; > c = a - b; > } > > I then used the following command: > llc -march=lacore -debug -print-after-all main.bc -o main.s > > The program terminated with an assertion violation, see output below. > The UNDEF node (t3) apparently causes the problem. But, according to my > understanding, this node is already generated in the IR->DAG translation > and already exisiting in the initial selection DAG (in the load and > store commands).You program is loading from unallocated memory, this is what the "undef" represents here.> Therefore, it is probably not related to my own, > error-prone target implementation.You target does not handle undef apparently. -- Mehdi> That makes the problem even harder to > understand. I could not find out where the UNDEF SDNode is generated. > > Thank you in advance for any hints! > > Best regards, > Markus > > --------------------------------------------------------------------- > ... > > *** IR Dump After Module Verifier *** > ; Function Attrs: nounwind uwtable > define void @main() #0 { > %a = alloca i32, align 4 > %b = alloca i32, align 4 > %c = alloca i32, align 4 > %1 = load volatile i32, i32* %a, align 4 > %2 = load volatile i32, i32* %b, align 4 > %3 = sub nsw i32 %1, %2 > store volatile i32 %3, i32* %c, align 4 > ret void > } > ---- Branch Probability Info : main ---- > > Computing probabilities for > > === main > Initial selection DAG: BB#0 'main:' > SelectionDAG has 11 nodes: > t2: i32 = Constant<0> > t0: ch = EntryToken > t4: i32,ch = load<Volatile LD4[%a]> t0, FrameIndex:i32<0>, undef:i32 > t6: i32,ch = load<Volatile LD4[%b]> t4:1, FrameIndex:i32<1>, undef:i32 > t7: i32 = sub t4, t6 > t9: ch = store<Volatile ST4[%c]> t6:1, t7, FrameIndex:i32<2>, undef:i32 > t10: ch = RetFlag t9 > > ... > > *** Final schedule *** > SU(2): t3: i32 = undef > > SU(4): t4: i32,ch = load<Volatile LD4[%a]> t0, FrameIndex:i32<0>, undef:i32 > > SU(5): t6: i32,ch = load<Volatile LD4[%b]> t4:1, FrameIndex:i32<1>, > undef:i32 > > SU(3): t7: i32 = sub t4, t6 > > SU(1): t9: ch = store<Volatile ST4[%c]> t6:1, t7, FrameIndex:i32<2>, > undef:i32 > > SU(0): t10: ch = RetFlag t9 > > > t3: i32 = undef > This target-independent node should have been selected! > UNREACHABLE executed at > /home/markus/llvm_inst/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp:889! > > > > -- > Prof. Dr.-Ing. Markus Weinhardt - Hochschule Osnabrück > Visiting Researcher at www.inesc-id.pt -ESDA, Lisbon/PT > mweinhardt at computer.org - Tel.nr. +49-(0)541-969 3445 > Postf. 1940, 49009 Osnabrück (Artilleriestr. 46, SB223) > http://www.ecs.hs-osnabrueck.de/weinhardt.html > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
Tim Northover via llvm-dev
2016-May-17 13:57 UTC
[llvm-dev] SDNode type UNDEF in new llvm-backend
On 16 May 2016 at 12:56, Markus Weinhardt via llvm-dev <llvm-dev at lists.llvm.org> wrote:> *** Final schedule *** > SU(2): t3: i32 = undef > > SU(4): t4: i32,ch = load<Volatile LD4[%a]> t0, FrameIndex:i32<0>, undef:i32It looks like no instruction selection has happened. By the time "Final schedule" gets decided, these should all be your machine's native instructions. Are you sure you've implemented XYZISelDAGToDAG::Select properly? Cheers. Tim.