jingu kang via llvm-dev
2016-Feb-11 09:59 UTC
[llvm-dev] Question about loading spilled register with fast register allocator
Hi All, I have a problem with loading spilled register. Let's look at the simple example as follows: Machine IR snippet: ... ADD --> it generates carry. ADDC --> it uses carry. ... The fast register allocator is enabled with "-O0" option and it generates load instruction for one of ADDC's operands spilled between ADD and ADDC. When I eliminates the frame index for the load instruction, the real offset of the frame index is bigger than load instruction's immediate field and I generate add instruction in order to make correct address for the stack slot. As a result, the carry bit is broken. I think I could store and load carry bit with scratch register or make a pass to force to reload register spilled at a specific place. But I would like to check whether there are existing ways or better ways to solve this problem. Could someone let me know about it? If I missed something, please let me know. Thanks, JinGu Kang
Quentin Colombet via llvm-dev
2016-Feb-11 17:00 UTC
[llvm-dev] Question about loading spilled register with fast register allocator
Hi JinGu, What you are suggesting is a perfectly valid solution. Depending on how much control you have on the code doing that insertion, you could try to move the reload instruction before the add. Another solution is to use an instruction that does not clobber the flags, if any. E.g., on X86, in that case we can use LEA. Hope this helps. Cheers, -Quentin> On Feb 11, 2016, at 1:59 AM, jingu kang via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi All, > > I have a problem with loading spilled register. Let's look at the > simple example as follows: > > Machine IR snippet: > ... > ADD --> it generates carry. > ADDC --> it uses carry. > ... > > The fast register allocator is enabled with "-O0" option and it > generates load instruction for one of ADDC's operands spilled between > ADD and ADDC. When I eliminates the frame index for the load > instruction, the real offset of the frame index is bigger than load > instruction's immediate field and I generate add instruction in order > to make correct address for the stack slot. As a result, the carry bit > is broken. I think I could store and load carry bit with scratch > register or make a pass to force to reload register spilled at a > specific place. But I would like to check whether there are existing > ways or better ways to solve this problem. Could someone let me know > about it? If I missed something, please let me know. > > Thanks, > JinGu Kang > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
jingu kang via llvm-dev
2016-Feb-11 22:51 UTC
[llvm-dev] Question about loading spilled register with fast register allocator
Hi Quentin, I appreciate your response. Unfortunately, the target I am working does not have instruction like LEA. I thought it is not easy to move the reload instruction ahead of 'add' instruction after register allocation because the destination register of reload instructions could affect registers of add's operands. If there are consecutive 'addc' instructions, It could be harder. I thought a machine function pass before register allocation. The pass simply checks whether 'addc' instruction's operands are first use. If so, it adds dummy pseudo instructions, which use the operands, ahead of 'add' instruction. As a result, fast register allocator generates reload instruction ahead of the copy instruction. I thought it is trick but it would work. How do you feel about it? Thanks, JinGu Kang 2016-02-11 17:00 GMT+00:00 Quentin Colombet <qcolombet at apple.com>:> Hi JinGu, > > What you are suggesting is a perfectly valid solution. > Depending on how much control you have on the code doing that insertion, you could try to move the reload instruction before the add. > Another solution is to use an instruction that does not clobber the flags, if any. E.g., on X86, in that case we can use LEA. > > Hope this helps. > > Cheers, > -Quentin >> On Feb 11, 2016, at 1:59 AM, jingu kang via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> Hi All, >> >> I have a problem with loading spilled register. Let's look at the >> simple example as follows: >> >> Machine IR snippet: >> ... >> ADD --> it generates carry. >> ADDC --> it uses carry. >> ... >> >> The fast register allocator is enabled with "-O0" option and it >> generates load instruction for one of ADDC's operands spilled between >> ADD and ADDC. When I eliminates the frame index for the load >> instruction, the real offset of the frame index is bigger than load >> instruction's immediate field and I generate add instruction in order >> to make correct address for the stack slot. As a result, the carry bit >> is broken. I think I could store and load carry bit with scratch >> register or make a pass to force to reload register spilled at a >> specific place. But I would like to check whether there are existing >> ways or better ways to solve this problem. Could someone let me know >> about it? If I missed something, please let me know. >> >> Thanks, >> JinGu Kang >> _______________________________________________ >> LLVM Developers mailing list >> llvm-dev at lists.llvm.org >> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >
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