llvm dev - Jun 2015 - [LLVMdev] Register Allocation on IR

Thanks. I will also work on doing an SSA register allocation that returns
SSA form (IR), since it is not yet implemented.

On Fri, Jun 12, 2015 at 9:20 PM, Matthias Braun <mbraun at apple.com>
wrote:
> llvm uses three different representations until machine code is emitted:
>
> - the llvm language as specified in the llvm manuals, we usually call that
> IR
> - the selection DAG
> - machine code, which is often called MI
>
> llvm currently only has infrastructure to serialize the first one.
> Register allocation only makes sense on the MI representation (before that
> we have no knowledge about register class or constraints, let alone which
> machine instructions will be used). Unfortunately MI cannot be serialized
> at the moment, although I think Alex Lorenz is currently working on adding
> this.
>
> - Matthias
>
> On Jun 12, 2015, at 11:00 AM, kartikram3 <kartikram3 at gmail.com>
wrote:
>
> Hello all,
>
>   I am trying to use the LLVM libraries to do register allocation on LLVM
> IR code -- and output IR as the result.
> There are two problems that arise when we try this :
>
> a. The LLVM backend requires that one goes through all the steps
> sequentially namely
>
>      -- Instruction selection
>      -- Scheduling and Formation
>      -- SSA-based machine code optimizations
>      -- Register allocations
>
>
>        ...
>
>
>       -- Code emission
>
> Is it possible to emit IR from the 1st 3 stages and then do register
> allocation on it ?
> Normally, we would emit assembly based on the machine/ISA specifications
> during
> instruction selection.
>
> b. I have llvm IR in the form of a DAG already. This was obtained by using
> the llvm;;parseIRFile
> function. I am not sure how to provide this ISA as an input to the backend
> phases as they
> seem to accept all kinds of other objects.
>
> Are there any llvm functions that accept a DAG as input so that we can do
> register allocation on it
> subsequently ?
>
>
> Note : This might look like a weird thing to do, but I want to do
> simulations on IR and getting a
> register-allocated IR is useful for that purpose.
>
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On 15 Jun 2015, at 17:21, Kartik Ramkrishnan <kartikram3 at gmail.com>
wrote:
> 
> Thanks. I will also work on doing an SSA register allocation that returns
SSA form (IR), since it is not yet implemented.
It’s not implemented because it doesn’t really make sense as a concept. 
Register allocation is all about making use of a finite set of registers,
spilling values to memory if they don’t fit.  In SSA form, you have an infinite
number of registers and (more importantly) you can only assign to each register
once, so there is no way of spilling from a register and then using that
register for something else.

To implement register allocation in LLVM IR, you would need IR not to be SSA,
and then it wouldn’t be LLVM IR.

David

Having worked on SSA register allocators in the past I have to say that SSA is
actually a good fit for register allocation. However LLVM IR is indeed not. You
don't have any target instructions or register classed/constraints. It
wouldn't make much sense to designate registers to llvm IR values nor is
there a way to express that in IR. llvm has the machine instruction (MI)
representation for that.

- Matthias
> On Jun 17, 2015, at 5:37 AM, David Chisnall <David.Chisnall at
cl.cam.ac.uk> wrote:
> 
> On 15 Jun 2015, at 17:21, Kartik Ramkrishnan <kartikram3 at
gmail.com> wrote:
>> 
>> Thanks. I will also work on doing an SSA register allocation that
returns SSA form (IR), since it is not yet implemented.
> 
> It’s not implemented because it doesn’t really make sense as a concept. 
Register allocation is all about making use of a finite set of registers,
spilling values to memory if they don’t fit.  In SSA form, you have an infinite
number of registers and (more importantly) you can only assign to each register
once, so there is no way of spilling from a register and then using that
register for something else.
> 
> To implement register allocation in LLVM IR, you would need IR not to be
SSA, and then it wouldn’t be LLVM IR.
> 
> David
>