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...ve no knowledge about register class or constraints, let alone which > machine instructions will be used). Unfortunately MI cannot be serialized > at the moment, although I think Alex Lorenz is currently working on adding > this. > > - Matthias > > On Jun 12, 2015, at 11:00 AM, kartikram3 <kartikram3 at gmail.com> wrote: > > Hello all, > > I am trying to use the LLVM libraries to do register allocation on LLVM > IR code -- and output IR as the result. > There are two problems that arise when we try this : > > a. The LLVM backend requires that one goes...

Hello all, I am trying to use the LLVM libraries to do register allocation on LLVM IR code -- and output IR as the result. There are two problems that arise when we try this : a. The LLVM backend requires that one goes through all the steps sequentially namely -- Instruction selection -- Scheduling and Formation -- SSA-based machine code optimizations -- Register

...egisters to llvm IR values nor is there a way to express that in IR. llvm has the machine instruction (MI) representation for that. - Matthias > On Jun 17, 2015, at 5:37 AM, David Chisnall <David.Chisnall at cl.cam.ac.uk> wrote: > > On 15 Jun 2015, at 17:21, Kartik Ramkrishnan <kartikram3 at gmail.com> wrote: >> >> Thanks. I will also work on doing an SSA register allocation that returns SSA form (IR), since it is not yet implemented. > > It’s not implemented because it doesn’t really make sense as a concept. Register allocation is all about making use of a f...