Displaying 1 result from an estimated 1 matches for "dd652ab9".
2015 Jun 17
3
[LLVMdev] Register Allocation on IR
Having worked on SSA register allocators in the past I have to say that SSA is actually a good fit for register allocation. However LLVM IR is indeed not. You don't have any target instructions or register classed/constraints. It wouldn't make much sense to designate registers to llvm IR values nor is there a way to express that in IR. llvm has the machine instruction (MI) representation