Hi, How do "Pat" operands get matched? I am trying to follow the example given in http://llvm.org/docs/CodeGenerator.html#selectiondag-process In the latest trunk of ppcintrinfo.td following pattern is defined: def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), (STWU $rS, iaddroff:$ptroff, $ptrreg)>; I understand that input operand list i.e. ins of stwu should get matched with the given pre_store. But I am confused as to how "ptroff" and "ptrreg" get matched with "memri" used in STWU? For reference[1] memri is defined as: def memri :Operand<iPTR> { let PrintMethod = "printMemRegImm"; let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); let EncoderMethod = "getMemRIEncoding";} [1] https://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?view=markup -- * Anitha* -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130407/e6eb650a/attachment.html>
Hi Anitha, memri is just describing that the address contains two components, an immediate and a register, and how to handle them in the instruction printer. The STWU expects a memri operand, and that is what is passed from the Pat. Hope that helps, Sam On 07/04/2013 10:19, Anitha B Gollamudi wrote:> Hi, > > > How do "Pat" operands get matched? I am trying to follow the example > given in http://llvm.org/docs/CodeGenerator.html#selectiondag-process > > In the latest trunk of ppcintrinfo.td <http://ppcintrinfo.td> > following pattern is defined: > > def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), > (STWU $rS, iaddroff:$ptroff, $ptrreg)>; > > I understand that input operand list i.e. ins of stwu should get > matched with the given pre_store. But I am confused as to how > "ptroff" and "ptrreg" get matched with "memri" used in STWU? > > > For reference[1] memri is defined as: > > def memri :Operand<iPTR> { > > let PrintMethod = "printMemRegImm"; > > let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); > > let EncoderMethod = "getMemRIEncoding"; > > } > > [1] > https://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?view=markup > -- > /* Anitha*/ > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130407/2eb12724/attachment.html>
On 7 April 2013 14:54, Sam Parker <S.Parker3 at lboro.ac.uk> wrote:> Hi Anitha, > > memri is just describing that the address contains two components, an > immediate and a register, and how to handle them in the instruction printer. > The STWU expects a memri operand, and that is what is passed from the Pat. >My confusion is how operands of STWU from "Pat pre_store" get matched with those of memri. It is defined with operand types as: let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); while Pat is defined as: def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), (STWU $rS, iaddroff:$ptroff, $ptrreg)>; So now how iPTR:$ptrreg and iaddroff:$ptroff get matched with ptr_rc_nor0:$reg and dispRI:$imm respectively? I mean the types are not exactly matching. Probably something is amiss in my understanding. -Anitha> > On 07/04/2013 10:19, Anitha B Gollamudi wrote: > > Hi, > > > How do "Pat" operands get matched? I am trying to follow the example given > in http://llvm.org/docs/CodeGenerator.html#selectiondag-process > > In the latest trunk of ppcintrinfo.td following pattern is defined: > > def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), > (STWU $rS, iaddroff:$ptroff, $ptrreg)>; > > I understand that input operand list i.e. ins of stwu should get matched > with the given pre_store. But I am confused as to how "ptroff" and "ptrreg" > get matched with "memri" used in STWU? > > > For reference[1] memri is defined as: > > def memri :Operand<iPTR> { > > let PrintMethod = "printMemRegImm"; > > let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); > > let EncoderMethod = "getMemRIEncoding"; > } > > [1] > https://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?view=markup > -- > Anitha > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >-- Anitha
Seemingly Similar Threads
- [LLVMdev] Pat operands matching example in ppc
- [LLVMdev] Pat operands matching example in ppc
- [LLVMdev] tablegen and ptr_rc: PointerLikeRegClass
- [LLVMdev] Post Increment Indirect Move Instructions
- [LLVMdev] "Unknown node flavor ..." Was: Re: tablegen and ptr_rc: PointerLikeRegClass