search for: memri

..._store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), (STWU $rS, iaddroff:$ptroff, $ptrreg)>; I understand that input operand list i.e. ins of stwu should get matched with the given pre_store. But I am confused as to how "ptroff" and "ptrreg" get matched with "memri" used in STWU? For reference[1] memri is defined as: def memri :Operand<iPTR> { let PrintMethod = "printMemRegImm"; let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); let EncoderMethod = "getMemRIEncoding";} [1] https://llvm.org/viewvc/llvm-project/llvm/...

Hi Anitha, memri is just describing that the address contains two components, an immediate and a register, and how to handle them in the instruction printer. The STWU expects a memri operand, and that is what is passed from the Pat. Hope that helps, Sam On 07/04/2013 10:19, Anitha B Gollamudi wrote: > Hi, &...

On 7 April 2013 14:54, Sam Parker <S.Parker3 at lboro.ac.uk> wrote: > Hi Anitha, > > memri is just describing that the address contains two components, an > immediate and a register, and how to handle them in the instruction printer. > The STWU expects a memri operand, and that is what is passed from the Pat. > My confusion is how operands of STWU from "Pat pre_store"...

in llvm-3.6.2.src 1. when I put this around one of my instruction definitions in my target "InstrInfo.td" file, let TwoOperandAliasConstraint = "$dst = $rs1" in { } I do not see any TIED_TO in the generated GenInstrInfo.inc file for the OperandInfo used by the instruction, the question is what am I doing wrong ? 2. I've noticed that TwoOperandAliasConstraint

...tly there than in PowerPC/PPCInstr64Bit.td > > > Thoughts/comments/suggestions? I've been poking at this a bit more, and have tried wrapping the ptr_rc within a larger blob; I'm getting different error messages out, but can't tell whether or not this is progress. Using the memri definitions as inspiration: +def ptr_rc_wrapper : Operand<iPTR> { + let PrintMethod = "printMemRegImm"; + let MIOperandInfo = (ops ptr_rc:$ea_result); +} And then swapping out the ptr_rc: references like so: -def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins mem...

Hi all, I've been poking at AsmParser support for powerpc64 (ppc64-elf-linux-abi) and have run into some behavior I don't understand with the ptr_rc references coming out of the PPC*.td files when generating the asm-matcher files. For instance : $ ./build/bin/llvm-tblgen llvm/lib/Target/PowerPC/PPC.td -I ~/llvm-head/llvm/include -I ~/llvm-head/llvm/lib/Target/PowerPC/ -gen-asm-matcher

...., in lisp: > (+ 1 2) 3 > * 3 I wish I could recover the value of the last expression without re-evaluating it. thanks -- Sam Steingold (http://sds.podval.org/) on Ubuntu 11.10 (oneiric) X 11.0.11004000 http://www.childpsy.net/ http://camera.org http://ffii.org http://truepeace.org http://memri.org http://americancensorship.org The early bird may get the worm, but the second mouse gets the cheese.

...urned into a factor inside sapply(), but after that it is numerical again! what am I doing wrong? -- Sam Steingold (http://www.podval.org/~sds) on Fedora Core release 5 (Bordeaux) http://honestreporting.com http://truepeace.org http://openvotingconsortium.org http://thereligionofpeace.com http://memri.org http://palestinefacts.org UNIX, car: hard to learn/easy to use; Windows, bike: hard to learn/hard to use.

...gister call AddrRegs 2) I registered the class AddrRegs (addRegisterClass(MVT::iPTR, .. )) 3) I added method addPointerRegClass() to my InstrInfo class The compiler generates the some code as before, but that seems to be ok, because I haven't used ptr_rc yet. 4) I changed the address mode MEMri: def MEMri : Operand<iPTR> { let PrintMethod = "printMemOperand"; // was: let MIOperandInfo = (ops IntRegs, i32imm); let MIOperandInfo = (ops ptr_rc, i32imm); } for the C code int c; void f(void) { c = 4711; } I get the error message: Register class of operand and regc...

Hello > Finally, I don't know how to describe following instructions in > MCoreInstrInfo.td, because of its variable ins/outs. Or what other files > should I use to finish this description? Do you need the isel support for them? If yes, then you should custom isel them. iirc ARM and SystemZ backends have similar instructions, while only the first one supports full isel for them. In

...t;---------------cut here---------------end--------------->8--- thanks! -- Sam Steingold (http://sds.podval.org/) on Ubuntu 12.04 (precise) X 11.0.11103000 http://www.childpsy.net/ http://palestinefacts.org http://dhimmi.com http://jihadwatch.org http://www.PetitionOnline.com/tap12009/ http://memri.org Rhinoceros has poor vision, but, due to his size, it's not his problem.

...ter+constant addressing mode. Then, I have DAG like: (store ..., (frameindex)) Targets like SPARC have the following patterns to catch this: def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>; def STri : F3_2<3, 0b000100, (outs), (ins MEMri:$addr, IntRegs:$src), "st $src, [$addr]", [(store IntRegs:$src, ADDRri:$addr)]>; Where ADDRri will eventually turn into register+constant addressing in assembler. The IA64 target has explicit case in it's Select method to handle frameindex -- whi...

...## don't want ".1"! 1 6843 > tab 0 1 2344600 6843 --8<---------------cut here---------------end--------------->8--- -- Sam Steingold (http://sds.podval.org/) on Ubuntu 12.04 (precise) X 11.0.11103000 http://www.childpsy.net/ http://pmw.org.il http://memri.org http://ffii.org http://openvotingconsortium.org Islam is a religion of Peace. Its adherents will kill anyone who disagrees.

...constraint to some instructions where the src and dest regs can't be the same. The offending instruction pattern is this one: let canFoldAsLoad = 1, isReMaterializable = 1, Constraints = "@earlyclobber $dst" in def LDDWRdPtrQ : Inst<(outs DREGS:$dst), (ins memri:$src), "lddw\t$dst, $src", [(set DREGS:$dst, (load addr:$src))]>; This is just a load with displacement instruction of the form "load reg, [reg_addr+<offs>]", where reg_addr and dest can't be the same register. This...

...t; > > > > > Thoughts/comments/suggestions? > > I've been poking at this a bit more, and have tried wrapping the ptr_rc > within a larger blob; I'm getting different error messages out, but > can't tell whether or not this is progress. > > Using the memri definitions as inspiration: > +def ptr_rc_wrapper : Operand<iPTR> { > + let PrintMethod = "printMemRegImm"; > + let MIOperandInfo = (ops ptr_rc:$ea_result); > +} > > And then swapping out the ptr_rc: references like so: > > -def LBZU : DForm_1<35, (out...

...raph.data.frame accepts data.frame as the first argument. the igraph maintainers say that "it is not coming from igraph". thanks. -- Sam Steingold (http://sds.podval.org/) on Ubuntu 12.10 (quantal) X 11.0.11300000 http://www.childpsy.net/ http://www.PetitionOnline.com/tap12009/ http://memri.org http://thereligionofpeace.com http://jihadwatch.org Growing Old is Inevitable; Growing Up is Optional.

...egs:$dst, IntRegs:$dst2), >> >> // Load doubleword conditionally. >> let mayLoad = 1, neverHasSideEffects = 1 in >> -def LDrid_cPt : LDInst<(outs DoubleRegs:$dst), >> +def LDrid_cPt : LDInst2<(outs DoubleRegs:$dst), >> (ins PredRegs:$src1, MEMri:$addr), >> "if ($src1) $dst = memd($addr)", >> []>; >> >> >> let mayLoad = 1, neverHasSideEffects = 1 in >> -def LDrid_cNotPt : LDInst<(outs DoubleRegs:$dst), >> +def LDrid_cNotPt : LDInst2<(outs DoubleRegs:$...

...ns where the src and dest regs can't be the same. The offending instruction pattern is this one: > > let canFoldAsLoad = 1, > isReMaterializable = 1, > Constraints = "@earlyclobber $dst" in > def LDDWRdPtrQ : Inst<(outs DREGS:$dst), > (ins memri:$src), > "lddw\t$dst, $src", > [(set DREGS:$dst, (load addr:$src))]>; > > This is just a load with displacement instruction of the form "load reg, [reg_addr+<offs>]", where reg_addr and dest can't be the s...

...ere---------------end--------------->8--- I want the vector TRUE,FALSE,FALSE,FALSE selecting just the first row because there all 3 columns are the same and none is NA. thanks! -- Sam Steingold (http://sds.podval.org/) on Ubuntu 12.04 (precise) X 11.0.11103000 http://www.childpsy.net/ http://memri.org http://mideasttruth.com http://honestreporting.com http://pmw.org.il http://iris.org.il All extremists should be taken out and shot.

...: cannot coerce class '"rle"' into a data.frame it seems that rle.df <- data.frame(values=rle$values,length=rle$length) works and DTRT. -- Sam Steingold (http://sds.podval.org/) on Ubuntu 12.04 (precise) X 11.0.11103000 http://www.childpsy.net/ http://iris.org.il http://memri.org http://www.PetitionOnline.com/tap12009/ http://camera.org char*a="char*a=%c%s%c;main(){printf(a,34,a,34);}";main(){printf(a,34,a,34);}