llvm dev - Feb 2011 - [LLVMdev] TableGen syntax for matching a constant load

On Sat, Feb 26, 2011 at 01:07:39PM -0800, Jakob Stoklund Olesen
wrote:
> 
> On Feb 25, 2011, at 7:27 PM, Joerg Sonnenberger wrote:
> 
> > I'm trying to add a X86 pattern to turn
> > 	movl $-1, %eax
> > into
> > 	orl $-1, $eax
> 
> Please make sure to measure the performance impact of doing this. You
> are creating a false dependency on the last instruction to write %eax,
> and the CPU won't be able to execute the following instructions in
> parallel.
I am primarily interested in size here, not speed.
> You may want to consider using xorl+decl instead. It is also three
> bytes, and there are no false dependencies. The xor idiom is recognized
> by processors as old as Pentium 4 as having no dependencies.
Any examples of how to create more than one instructions for a given
pattern? There are some other cases I could use this for.

Joerg

On Feb 26, 2011, at 1:36 PM, Joerg Sonnenberger wrote:
> On Sat, Feb 26, 2011 at 01:07:39PM -0800, Jakob Stoklund Olesen wrote:
>> 
>> You may want to consider using xorl+decl instead. It is also three
>> bytes, and there are no false dependencies. The xor idiom is recognized
>> by processors as old as Pentium 4 as having no dependencies.
> 
> Any examples of how to create more than one instructions for a given
> pattern? There are some other cases I could use this for.
def : Pat<(i32 -1), (DEC32r (MOV32r0))>;

/jakob


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On Sat, Feb 26, 2011 at 02:04:54PM -0800, Jakob Stoklund Olesen
wrote:
> 
> On Feb 26, 2011, at 1:36 PM, Joerg Sonnenberger wrote:
> 
> > On Sat, Feb 26, 2011 at 01:07:39PM -0800, Jakob Stoklund Olesen wrote:
> >> 
> >> You may want to consider using xorl+decl instead. It is also three
> >> bytes, and there are no false dependencies. The xor idiom is
recognized
> >> by processors as old as Pentium 4 as having no dependencies.
> > 
> > Any examples of how to create more than one instructions for a given
> > pattern? There are some other cases I could use this for.
> 
> def : Pat<(i32 -1), (DEC32r (MOV32r0))>;
Hm. Right. This gives the me first set of size peep hole optmisations as
attached. I didn't add the above rule for 64bit builds, since it is
larger than the to-be-figured out OR32rmi8 / OR64rmi8.

Joerg
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