Displaying 5 results from an estimated 5 matches for "or64mi8".
2011 Feb 27
0
[LLVMdev] TableGen syntax for matching a constant load
...b 27, 2011 at 01:29:25AM +0100, Joerg Sonnenberger wrote:
> +let Predicates = [OptForSize] in {
> +def : Pat<(store (i32 0), addr:$dst), (AND32mi8 addr:$dst, 0)>;
> +def : Pat<(store (i32 0), addr:$dst), (AND32mi8 addr:$dst, 0)>;
> +def : Pat<(store (i64 -1), addr:$dst), (OR64mi8 addr:$dst, -1)>;
> +def : Pat<(store (i64 -1), addr:$dst), (OR64mi8 addr:$dst, -1)>;
> +}
All these patterns have one important downside. They are suboptimal if
more than one store happens in a row. E.g. the 0 store is better
expressed as xor followed by two register moves, if a reg...
2011 Feb 27
2
[LLVMdev] TableGen syntax for matching a constant load
On Sat, Feb 26, 2011 at 02:04:54PM -0800, Jakob Stoklund Olesen wrote:
>
> On Feb 26, 2011, at 1:36 PM, Joerg Sonnenberger wrote:
>
> > On Sat, Feb 26, 2011 at 01:07:39PM -0800, Jakob Stoklund Olesen wrote:
> >>
> >> You may want to consider using xorl+decl instead. It is also three
> >> bytes, and there are no false dependencies. The xor idiom is
2015 Aug 16
2
[LLVMdev] Adding a stack probe function attribute
...#4
%EAX<def> = MOV32ri 40040; flags: FrameSetup
%RDX<def> = MOV64rr %RAX; flags: FrameSetup
%RCX<def> = MOV64rr %RSP; flags: FrameSetup
Successors according to CFG: BB#1
BB#1: derived from LLVM BB %0
Predecessors according to CFG: BB#0 BB#1
OR64mi8 %RCX, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>;
flags: FrameSetup
%RCX<def,tied1> = SUB64ri32 %RCX<tied0>, 4096,
%EFLAGS<imp-def>; flags: FrameSetup
%RDX<def,tied1> = SUB64ri32 %RDX<tied0>, 4096,
%EFLAGS<imp-def>; flags: FrameSetup...
2015 Jul 28
1
[LLVMdev] Adding a stack probe function attribute
On Tue, Jul 28, 2015 at 6:34 PM, Reid Kleckner <rnk at google.com> wrote:
> On Tue, Jul 28, 2015 at 2:25 AM, John Kåre Alsaker
> <john.mailinglists at gmail.com> wrote:
>>
>> On Tue, Jul 28, 2015 at 12:44 AM, Reid Kleckner <rnk at google.com> wrote:
>> > Yeah, the function attributes section of LangRef is a reasonable place
>> > to
>>
2011 Feb 27
3
[LLVMdev] TableGen syntax for matching a constant load
...:29:25AM +0100, Joerg Sonnenberger wrote:
>> +let Predicates = [OptForSize] in {
>> +def : Pat<(store (i32 0), addr:$dst), (AND32mi8 addr:$dst, 0)>;
>> +def : Pat<(store (i32 0), addr:$dst), (AND32mi8 addr:$dst, 0)>;
>> +def : Pat<(store (i64 -1), addr:$dst), (OR64mi8 addr:$dst, -1)>;
>> +def : Pat<(store (i64 -1), addr:$dst), (OR64mi8 addr:$dst, -1)>;
>> +}
>
> All these patterns have one important downside. They are suboptimal if
> more than one store happens in a row. E.g. the 0 store is better
> expressed as xor followed by...