llvm dev - Apr 2018 - llvm-dev Digest, Vol 166, Issue 22

Hi Krzysztof,

Sure, please see below. DAG.dump.() before and after, annotated with what I
believe the DAG means.

I've spent some time debugging the method but it's proving difficult to
determine where the logic is misfiring. Disabling the entire combine causes
a lot of failing x86-64 tests - I may have to learn an upstream vector ISA
to make progress on this.

Thank you

>From your description it seems like you are seeing an incorrect
behavior. If that's the case, it should definitely be fixed. Could you
provide the complete DAG before and after the erroneous transformation?

-Krzysztof

Combining: t25: v2i16 = BUILD_VECTOR t27, t22

Before reduceBuildVecToShuffle

SelectionDAG has 14 nodes:

  t0: ch = EntryToken

  t2: v4i16,ch = CopyFromReg t0, Register:v4i16 %0 // [a b c d]

        t26: v2i16 = extract_subvector t2, Constant:i32<0> // [a b]

      t27: i16 = extract_vector_elt t26, Constant:i32<0> // [a]

        t21: v2i16 = extract_subvector t2, Constant:i32<2> //[c d]

      t22: i16 = extract_vector_elt t21, Constant:i32<0> // [c]

    t25: v2i16 = BUILD_VECTOR t27, t22 // [a c]

  t18: ch,glue = CopyToReg t0, Register:v2i16 %m0, t25

    t19: ch = RTN t18

  t20: ch = RTN_REG_HOLDER t19, Register:v2i16 %m0, t18:1





Creating new node: t28: v2i16 = undef

Creating new node: t29: v2i16 = vector_shuffle<0,0> t26, undef:v2i16

After reduceBuildVecToShuffle

SelectionDAG has 16 nodes:

  t0: ch = EntryToken

  t2: v4i16,ch = CopyFromReg t0, Register:v4i16 %0 // [a b c d]

      t27: i16 = extract_vector_elt t26, Constant:i32<0>

        t21: v2i16 = extract_subvector t2, Constant:i32<2>

      t22: i16 = extract_vector_elt t21, Constant:i32<0>

    t25: v2i16 = BUILD_VECTOR t27, t22

  t18: ch,glue = CopyToReg t0, Register:v2i16 %m0, t25

  t26: v2i16 = extract_subvector t2, Constant:i32<0> // [a b]

  t29: v2i16 = vector_shuffle<0,0> t26, undef:v2i16 // [a a]

    t19: ch = RTN t18

  t20: ch = RTN_REG_HOLDER t19, Register:v2i16 %m0, t18:1





... into: t29: v2i16 = vector_shuffle<0,0> t26, undef:v2i16
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The node t29 seems to be dead. The CopyToReg m0 still uses t25, same as 
the original code.

Does t29 disappear later on?

-Krzysztof

On 4/9/2018 11:25 AM, Jon Chesterfield via llvm-dev
wrote:
> Hi Krzysztof,
> 
> Sure, please see below. DAG.dump.() before and after, annotated with 
> what I believe the DAG means.
> 
> I've spent some time debugging the method but it's proving
difficult to
> determine where the logic is misfiring. Disabling the entire combine 
> causes a lot of failing x86-64 tests - I may have to learn an upstream 
> vector ISA to make progress on this.
> 
> Thank you
> 
> 
>  From your description it seems like you are seeing an incorrect
> behavior. If that's the case, it should definitely be fixed. Could you
> provide the complete DAG before and after the erroneous transformation?
> 
> -Krzysztof
> 
> Combining: t25: v2i16 = BUILD_VECTOR t27, t22
> 
> Before reduceBuildVecToShuffle____
> 
> SelectionDAG has 14 nodes:____
> 
>    t0: ch = EntryToken____
> 
>    t2: v4i16,ch = CopyFromReg t0, Register:v4i16 %0 // [a b c d]____
> 
>          t26: v2i16 = extract_subvector t2, Constant:i32<0> // [a
b]____
> 
>        t27: i16 = extract_vector_elt t26, Constant:i32<0> // [a]____
> 
>          t21: v2i16 = extract_subvector t2, Constant:i32<2> //[c
d]____
> 
>        t22: i16 = extract_vector_elt t21, Constant:i32<0> // [c]____
> 
>      t25: v2i16 = BUILD_VECTOR t27, t22 // [a c]____
> 
>    t18: ch,glue = CopyToReg t0, Register:v2i16 %m0, t25____
> 
>      t19: ch = RTN t18____
> 
>    t20: ch = RTN_REG_HOLDER t19, Register:v2i16 %m0, t18:1____
> 
> __ __
> 
> __ __
> 
> Creating new node: t28: v2i16 = undef____
> 
> Creating new node: t29: v2i16 = vector_shuffle<0,0> t26,
undef:v2i16____
> 
> After reduceBuildVecToShuffle____
> 
> SelectionDAG has 16 nodes:____
> 
>    t0: ch = EntryToken____
> 
>    t2: v4i16,ch = CopyFromReg t0, Register:v4i16 %0 // [a b c d]____
> 
>        t27: i16 = extract_vector_elt t26, Constant:i32<0>____
> 
>          t21: v2i16 = extract_subvector t2, Constant:i32<2>____
> 
>        t22: i16 = extract_vector_elt t21, Constant:i32<0>____
> 
>      t25: v2i16 = BUILD_VECTOR t27, t22____
> 
>    t18: ch,glue = CopyToReg t0, Register:v2i16 %m0, t25____
> 
>    t26: v2i16 = extract_subvector t2, Constant:i32<0> // [a b]____
> 
>    t29: v2i16 = vector_shuffle<0,0> t26, undef:v2i16 // [a a]____
> 
>      t19: ch = RTN t18____
> 
>    t20: ch = RTN_REG_HOLDER t19, Register:v2i16 %m0, t18:1____
> 
> __ __
> 
> __ __
> 
> ... into: t29: v2i16 = vector_shuffle<0,0> t26, undef:v2i16
> 
> 
> 
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