From 56d4b02f595c75b3884b36e54c880ec7019680bc Mon Sep 17 00:00:00 2001
From: Liu Jinsong <jinsong.liu@intel.com>
Date: Fri, 8 Nov 2013 01:40:59 +0800
Subject: [PATCH 2/3] X86: MPX support for PV guest
Signed-off-by: Xudong Hao <xudong.hao@intel.com>
Acked-by: Liu Jinsong <jinsong.liu@intel.com>
---
tools/libxc/xc_cpuid_x86.c | 3 ++-
xen/arch/x86/traps.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
index bcb7a59..4c922a8 100644
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -504,7 +504,8 @@ static void xc_cpuid_pv_policy(
bitmaskof(X86_FEATURE_BMI2) |
bitmaskof(X86_FEATURE_ERMS) |
bitmaskof(X86_FEATURE_RTM) |
- bitmaskof(X86_FEATURE_FSGSBASE));
+ bitmaskof(X86_FEATURE_FSGSBASE) |
+ bitmaskof(X86_FEATURE_MPX));
else
regs[1] = 0;
regs[0] = regs[2] = regs[3] = 0;
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 77c200b..4ecf7d5 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -826,7 +826,8 @@ static void pv_cpuid(struct cpu_user_regs *regs)
cpufeat_mask(X86_FEATURE_BMI2) |
cpufeat_mask(X86_FEATURE_ERMS) |
cpufeat_mask(X86_FEATURE_RTM) |
- cpufeat_mask(X86_FEATURE_FSGSBASE));
+ cpufeat_mask(X86_FEATURE_FSGSBASE) |
+ cpufeat_mask(X86_FEATURE_MPX));
else
b = 0;
a = c = d = 0;
--
1.7.1
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>>> On 11.11.13 at 09:39, "Liu, Jinsong" <jinsong.liu@intel.com> wrote: > From 56d4b02f595c75b3884b36e54c880ec7019680bc Mon Sep 17 00:00:00 2001 > From: Liu Jinsong <jinsong.liu@intel.com> > Date: Fri, 8 Nov 2013 01:40:59 +0800 > Subject: [PATCH 2/3] X86: MPX support for PV guest > > Signed-off-by: Xudong Hao <xudong.hao@intel.com> > Acked-by: Liu Jinsong <jinsong.liu@intel.com> > > --- > tools/libxc/xc_cpuid_x86.c | 3 ++- > xen/arch/x86/traps.c | 3 ++- > 2 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c > index bcb7a59..4c922a8 100644 > --- a/tools/libxc/xc_cpuid_x86.c > +++ b/tools/libxc/xc_cpuid_x86.c > @@ -504,7 +504,8 @@ static void xc_cpuid_pv_policy( > bitmaskof(X86_FEATURE_BMI2) | > bitmaskof(X86_FEATURE_ERMS) | > bitmaskof(X86_FEATURE_RTM) | > - bitmaskof(X86_FEATURE_FSGSBASE)); > + bitmaskof(X86_FEATURE_FSGSBASE) | > + bitmaskof(X86_FEATURE_MPX)); > else > regs[1] = 0; > regs[0] = regs[2] = regs[3] = 0; > diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c > index 77c200b..4ecf7d5 100644 > --- a/xen/arch/x86/traps.c > +++ b/xen/arch/x86/traps.c > @@ -826,7 +826,8 @@ static void pv_cpuid(struct cpu_user_regs *regs) > cpufeat_mask(X86_FEATURE_BMI2) | > cpufeat_mask(X86_FEATURE_ERMS) | > cpufeat_mask(X86_FEATURE_RTM) | > - cpufeat_mask(X86_FEATURE_FSGSBASE)); > + cpufeat_mask(X86_FEATURE_FSGSBASE) | > + cpufeat_mask(X86_FEATURE_MPX)); > else > b = 0; > a = c = d = 0;So here you purely mechanically enable the feature. But did you consider how it would work? How is the MSR being handled? How do you switch between (guest) kernel and user mode? And there''s no word about what would need to be done when Xen wanted to use MPX for its own purposes too. In the shape it is now, the above is a clear NAK. Jan
Jan Beulich wrote:>>>> On 11.11.13 at 09:39, "Liu, Jinsong" <jinsong.liu@intel.com> wrote: >> From 56d4b02f595c75b3884b36e54c880ec7019680bc Mon Sep 17 00:00:00 >> 2001 From: Liu Jinsong <jinsong.liu@intel.com> >> Date: Fri, 8 Nov 2013 01:40:59 +0800 >> Subject: [PATCH 2/3] X86: MPX support for PV guest >> >> Signed-off-by: Xudong Hao <xudong.hao@intel.com> >> Acked-by: Liu Jinsong <jinsong.liu@intel.com> >> >> --- >> tools/libxc/xc_cpuid_x86.c | 3 ++- >> xen/arch/x86/traps.c | 3 ++- >> 2 files changed, 4 insertions(+), 2 deletions(-) >> >> diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c >> index bcb7a59..4c922a8 100644 --- a/tools/libxc/xc_cpuid_x86.c >> +++ b/tools/libxc/xc_cpuid_x86.c >> @@ -504,7 +504,8 @@ static void xc_cpuid_pv_policy( >> bitmaskof(X86_FEATURE_BMI2) | >> bitmaskof(X86_FEATURE_ERMS) | >> bitmaskof(X86_FEATURE_RTM) | >> - bitmaskof(X86_FEATURE_FSGSBASE)); >> + bitmaskof(X86_FEATURE_FSGSBASE) | >> + bitmaskof(X86_FEATURE_MPX)); else >> regs[1] = 0; >> regs[0] = regs[2] = regs[3] = 0; >> diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c >> index 77c200b..4ecf7d5 100644 >> --- a/xen/arch/x86/traps.c >> +++ b/xen/arch/x86/traps.c >> @@ -826,7 +826,8 @@ static void pv_cpuid(struct cpu_user_regs *regs) >> cpufeat_mask(X86_FEATURE_BMI2) | >> cpufeat_mask(X86_FEATURE_ERMS) | >> cpufeat_mask(X86_FEATURE_RTM) | >> - cpufeat_mask(X86_FEATURE_FSGSBASE)); >> + cpufeat_mask(X86_FEATURE_FSGSBASE) | >> + cpufeat_mask(X86_FEATURE_MPX)); >> else >> b = 0; >> a = c = d = 0; > > So here you purely mechanically enable the feature. But did you > consider how it would work? How is the MSR being handled? How > do you switch between (guest) kernel and user mode? And there''s > no word about what would need to be done when Xen wanted to > use MPX for its own purposes too. > > In the shape it is now, the above is a clear NAK. > > Jan[MPX can probably be enabled for HVM guests only anyway] Let''s do not expose MPX to PV. Thanks, Jinsong