flight 17719 xen-unstable real [real] chiark.greenend.org.uk/~xensrcts/logs/17719 Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: test-amd64-amd64-xl-qemut-win7-amd64 8 guest-saverestore fail REGR. vs. 17714 test-amd64-amd64-xl-qemuu-winxpsp3 8 guest-saverestore fail REGR. vs. 17713 test-amd64-i386-xend-winxpsp3 9 guest-localmigrate fail REGR. vs. 17714 test-amd64-amd64-xl-win7-amd64 8 guest-saverestore fail REGR. vs. 17714 test-amd64-i386-xl-win7-amd64 8 guest-saverestore fail REGR. vs. 17714 test-amd64-i386-xl-qemut-win7-amd64 8 guest-saverestore fail REGR. vs. 17714 test-amd64-amd64-xl-winxpsp3 8 guest-saverestore fail REGR. vs. 17714 test-amd64-amd64-xl-qemut-winxpsp3 8 guest-saverestore fail REGR. vs. 17714 test-amd64-i386-xl-qemut-winxpsp3-vcpus1 10 guest-saverestore.2 fail REGR. vs. 17714 test-amd64-i386-xend-qemut-winxpsp3 8 guest-saverestore fail REGR. vs. 17714 Tests which did not succeed, but are not blocking: test-amd64-amd64-xl-pcipt-intel 9 guest-start fail never pass test-amd64-i386-xl-winxpsp3-vcpus1 13 guest-stop fail never pass test-amd64-amd64-xl-qemuu-win7-amd64 13 guest-stop fail never pass version targeted for testing: xen 764012376a096a45bced88ee2ec1a6c17c6c22c7 baseline version: xen 26c35e5cb93a7b4dcde940620eb7ac1845ed6e5a ------------------------------------------------------------ People who touched revisions under test: Andrew Cooper <andrew.cooper3@citrix.com> Daniel De Graaf <dgdegra@tycho.nsa.gov> George Dunlap <george.dunlap@eu.citrix.com> (from a release perspective) Ian Campbell <ian.campbell@citrix.com> Jan Beulich <jbeulich@suse.com> Keir Fraser <keir@xen.org> Stefano Stabellini <stefano.stabellini@eu.citrix.com> Yang Zhang <yang.z.zhang@Intel.com> ------------------------------------------------------------ jobs: build-amd64 pass build-armhf pass build-i386 pass build-amd64-oldkern pass build-i386-oldkern pass build-amd64-pvops pass build-i386-pvops pass test-amd64-amd64-xl pass test-amd64-i386-xl pass test-amd64-i386-rhel6hvm-amd pass test-amd64-i386-qemut-rhel6hvm-amd pass test-amd64-i386-qemuu-rhel6hvm-amd pass test-amd64-amd64-xl-qemut-win7-amd64 fail test-amd64-i386-xl-qemut-win7-amd64 fail test-amd64-amd64-xl-qemuu-win7-amd64 fail test-amd64-amd64-xl-win7-amd64 fail test-amd64-i386-xl-win7-amd64 fail test-amd64-i386-xl-credit2 pass test-amd64-amd64-xl-pcipt-intel fail test-amd64-i386-rhel6hvm-intel pass test-amd64-i386-qemut-rhel6hvm-intel pass test-amd64-i386-qemuu-rhel6hvm-intel pass test-amd64-i386-xl-multivcpu pass test-amd64-amd64-pair pass test-amd64-i386-pair pass test-amd64-amd64-xl-sedf-pin pass test-amd64-amd64-pv pass test-amd64-i386-pv pass test-amd64-amd64-xl-sedf pass test-amd64-i386-xl-qemut-winxpsp3-vcpus1 fail test-amd64-i386-xl-winxpsp3-vcpus1 fail test-amd64-i386-xend-qemut-winxpsp3 fail test-amd64-amd64-xl-qemut-winxpsp3 fail test-amd64-amd64-xl-qemuu-winxpsp3 fail test-amd64-i386-xend-winxpsp3 fail test-amd64-amd64-xl-winxpsp3 fail ------------------------------------------------------------ sg-report-flight on woking.cam.xci-test.com logs: /home/xc_osstest/logs images: /home/xc_osstest/images Logs, config files, etc. are available at chiark.greenend.org.uk/~xensrcts/logs Test harness code can be found at xenbits.xensource.com/gitweb?p=osstest.git;a=summary Not pushing. ------------------------------------------------------------ commit 764012376a096a45bced88ee2ec1a6c17c6c22c7 Author: Daniel De Graaf <dgdegra@tycho.nsa.gov> Date: Thu Apr 18 17:01:45 2013 +0200 x86: remove IS_PRIV access check bypasses Several domctl functions dealing with rangesets contain a short-circuit bypass if the domain is privileged. Since the construction of domain 0 permits access to all I/O ranges, the call to irq_access_permitted will normally return true even without the IS_PRIV check, and the presence of the IS_PRIV check prevents the creation of a privileged domain without access to specific devices or IO memory ranges. Signed-off-by: Daniel De Graaf <dgdegra@tycho.nsa.gov> commit d8b5421f45c2b528bab1c8695271f99743b708fa Merge: e83d6b9... 545607e... Author: Ian Campbell <ian.campbell@citrix.com> Date: Thu Apr 18 15:15:26 2013 +0100 Merge branch ''staging'' of ssh://xenbits.xen.org/home/xen/git/xen into staging commit 545607eb3cfeb2abf5742d1bb869734f317fcfe5 Author: Jan Beulich <jbeulich@suse.com> Date: Thu Apr 18 16:11:23 2013 +0200 x86: fix various issues with handling guest IRQs - properly revoke IRQ access in map_domain_pirq() error path - don''t permit replacing an in use IRQ - don''t accept inputs in the GSI range for MAP_PIRQ_TYPE_MSI - track IRQ access permission in host IRQ terms, not guest IRQ ones (and with that, also disallow Dom0 access to IRQ0) This is CVE-2013-1919 / XSA-46. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> commit fdac9515607b757c044e7ef0d61b1453ef999b08 Author: Jan Beulich <jbeulich@suse.com> Date: Thu Apr 18 16:00:35 2013 +0200 x86: clear EFLAGS.NT in SYSENTER entry path ... as it causes problems if we happen to exit back via IRET: In the course of trying to handle the fault, the hypervisor creates a stack frame by hand, and uses PUSHFQ to set the respective EFLAGS field, but expects to be able to IRET through that stack frame to the second portion of the fixup code (which causes a #GP due to the stored EFLAGS having NT set). And even if this worked (e.g if we cleared NT in that path), it would then (through the fail safe callback) cause a #GP in the guest with the SYSENTER handler''s first instruction as the source, which in turn would allow guest user mode code to crash the guest kernel. Inject a #GP on the fake (NULL) address of the SYSENTER instruction instead, just like in the case where the guest kernel didn''t register a corresponding entry point. This is CVE-2013-1917 / XSA-44. Reported-by: Andrew Cooper <andrew.cooper3@citirx.com> Signed-off-by: Jan Beulich <jbeulich@suse.com> Tested-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Andrew Cooper <andrew.cooper3@citrix.com> commit e83d6b9432af603200f065b499b8e4b78e92842d Author: Ian Campbell <ian.campbell@citrix.com> Date: Wed Apr 17 13:52:34 2013 +0100 arm: vgic: fix race in vgic_vcpu_inject_irq The initial check for a still pending interrupt (!list_empty(&n->inflight)) needs to be covered by the vgic lock to avoid trying to insert the IRQ into the inflight list simultaneously on 2 pCPUS. Expand the area covered by the lock appropriately. Also consolidate the unlocks on the exit path into one location. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> commit 153c66d80275ca7d2d617c26743b61083ecfa936 Author: Ian Campbell <ian.campbell@citrix.com> Date: Wed Apr 17 13:52:33 2013 +0100 arm64: correct secondary CPU bringup The current cpuid is held in x22 not x12. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> commit 691835f2a10b41cce4664c5fe7046f49ad3e0535 Author: Ian Campbell <ian.campbell@citrix.com> Date: Wed Apr 17 13:52:32 2013 +0100 arm: gic: implement IPIs using SGI mechanism Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> commit 8d266f6b2c5c3d2d0da42f1e40ba1fb2ac8fdf1a Author: Yang Zhang <yang.z.zhang@Intel.com> Date: Thu Apr 18 11:36:28 2013 +0200 VMX: Use posted interrupt to deliver virutal interrupt Deliver virtual interrupt through posted way if posted interrupt is enabled. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> Reviewed-by: Jun Nakajima <jun.nakajima@intel.com> Acked-by: Keir Fraser <keir@xen.org> Acked-by: George Dunlap <george.dunlap@eu.citrix.com> (from a release perspective) commit 04015d6326f17e4aafb32593b94dac44b72ef4c1 Author: Yang Zhang <yang.z.zhang@Intel.com> Date: Thu Apr 18 11:35:43 2013 +0200 x86/HVM: Call vlapic_set_irq() to delivery virtual interrupt Move kick_vcpu into vlapic_set_irq. And call it to deliver virtual interrupt instead set vIRR directly. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> Acked-by: Keir Fraser <keir@xen.org> Acked-by: George Dunlap <george.dunlap@eu.citrix.com> (from a release perspective) commit d7dafa375bc13772e2e3274d975d544af4208939 Author: Yang Zhang <yang.z.zhang@Intel.com> Date: Thu Apr 18 11:34:49 2013 +0200 VMX: Add posted interrupt supporting Add the supporting of using posted interrupt to deliver interrupt. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> Reviewed-by: Jun Nakajima <jun.nakajima@intel.com> Acked-by: Keir Fraser <keir@xen.org> Acked-by: George Dunlap <george.dunlap@eu.citrix.com> (from a release perspective) commit 1c0ac49b1d6c3d54fc1f75661742a988ca7cf255 Author: Yang Zhang <yang.z.zhang@Intel.com> Date: Thu Apr 18 11:34:04 2013 +0200 VMX: Turn on posted interrupt bit in vmcs Turn on posted interrupt for vcpu if posted interrupt is avaliable. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> Reviewed-by: Jun Nakajima <jun.nakajima@intel.com> Acked-by: Keir Fraser <keir@xen.org> Acked-by: George Dunlap <george.dunlap@eu.citrix.com> (from a release perspective) commit b266924990af96ee47ee299e1b6bb87fac2e2548 Author: Yang Zhang <yang.z.zhang@Intel.com> Date: Thu Apr 18 11:32:02 2013 +0200 VMX: Detect posted interrupt capability Check whether the Hardware supports posted interrupt capability. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> Reviewed-by: Jun Nakajima <jun.nakajima@intel.com> Acked-by: Keir Fraser <keir@xen.org> Acked-by: George Dunlap <george.dunlap@eu.citrix.com> (from a release perspective) (qemu changes not included)