Andre Przywara
2011-Apr-15 12:16 UTC
[Xen-devel] [PATCH 0/5] svm: implement new DecodeAssist feature
Hi, newer AMD SVM implementations (starting with Bulldozer) have some additions to SVM called DecodeAssist. These bits improve and simplify the handling of some intercepts, now more information is provided in the VMCB already and saves us from decoding this information "manually". These new features are described in recent editions of the APM Vol.2 manual, chapter 15.33. The first patch moves some code from VMX into HVM to be later used by SVM. The second patch adds the newly defined bits to VMCB and CPUID. Patch 3 to 5 implement three parts of the feature set, more details in the specific emails. Please comment. All patches: Signed-off-by: Andre Przywara <andre.przywara@amd.com> Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Andre Przywara
2011-Apr-15 12:21 UTC
[Xen-devel] [PATCH 1/5] vmx/hvm: move mov-cr handling functions to generic HVM code
Currently the handling of CR accesses intercepts is done much differently in SVM and VMX. For future usage move the VMX part into the generic HVM path and use the exported functions. Signed-off-by: Andre Przywara <andre.przywara@amd.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Andre Przywara
2011-Apr-15 12:21 UTC
[Xen-devel] [PATCH 2/5] svm: add bit definitions for SVM DecodeAssist
Chapter 15.33 of recent APM Vol.2 manuals describe some additions to SVM called DecodeAssist. Add the newly added fields to the VMCB structure and name the associated CPUID bit. Signed-off-by: Andre Przywara <andre.przywara@amd.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Andre Przywara
2011-Apr-15 12:22 UTC
[Xen-devel] [PATCH 3/5] svm: implement instruction fetch part of DecodeAssist
Newer SVM implementations (Bulldozer) copy up to 15 bytes from the instruction stream into the VMCB when a #PF or #NPF exception is intercepted. This patch makes use of this information if available. This saves us from a) traversing the guest''s page tables, b) mapping the guest''s memory and c) copy the instructions from there into the hypervisor''s address space. This speeds up #NPF intercepts quite a lot and avoids cache and TLB trashing. Signed-off-by: Andre Przywara <andre.przywara@amd.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Andre Przywara
2011-Apr-15 12:23 UTC
[Xen-devel] [PATCH 4/5] svm: implement CR access part of DecodeAssist
Newer SVM implementations (Bulldozer) now give the used general purpose register on a MOV-CR intercept explictly. This avoids fetching and decoding the instruction from guest''s memory and speeds up some Windows guest, which exercise CR8 quite often. Signed-off-by: Andre Przywara <andre.przywara@amd.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Andre Przywara
2011-Apr-15 12:24 UTC
[Xen-devel] [PATCH 5/5] svm: implement INVLPG part of DecodeAssist
Newer SVM implementations (Bulldozer) give the desired address on a INVLPG intercept explicitly in the EXITINFO1 field of the VMCB. Use this address to avoid a costly instruction fetch and deocde cycle. Only useful with shadow paging. Signed-off-by: Andre Przywara <andre.przywara@amd.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Keir Fraser
2011-Apr-18 08:48 UTC
Re: [Xen-devel] [PATCH 1/5] vmx/hvm: move mov-cr handling functions to generic HVM code
On 15/04/2011 13:21, "Andre Przywara" <andre.przywara@amd.com> wrote:> Currently the handling of CR accesses intercepts is done much > differently in SVM and VMX. For future usage move the VMX part > into the generic HVM path and use the exported functions.Cleaned up and applied as c/s 23233. In particular it broke VMX, by not preoperly decoding the GPR component of the exit qualification before passing to the new generic handler. -- Keir> Signed-off-by: Andre Przywara <andre.przywara@amd.com> > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xensource.com > http://lists.xensource.com/xen-devel_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Keir Fraser
2011-Apr-18 09:07 UTC
Re: [Xen-devel] [PATCH 5/5] svm: implement INVLPG part of DecodeAssist
On 15/04/2011 13:24, "Andre Przywara" <andre.przywara@amd.com> wrote:> Newer SVM implementations (Bulldozer) give the desired address on > a INVLPG intercept explicitly in the EXITINFO1 field of the VMCB. > Use this address to avoid a costly instruction fetch and deocde > cycle. > Only useful with shadow paging.Applied as c/2 23236. Fixed to not handle the INVLPGA exit code. -- Keir> Signed-off-by: Andre Przywara <andre.przywara@amd.com> > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xensource.com > http://lists.xensource.com/xen-devel_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Keir Fraser
2011-Apr-18 09:10 UTC
Re: [Xen-devel] [PATCH 3/5] svm: implement instruction fetch part of DecodeAssist
On 15/04/2011 13:22, "Andre Przywara" <andre.przywara@amd.com> wrote:> Newer SVM implementations (Bulldozer) copy up to 15 bytes from the > instruction stream into the VMCB when a #PF or #NPF exception is > intercepted. This patch makes use of this information if available. > This saves us from a) traversing the guest''s page tables, b) mapping > the guest''s memory and c) copy the instructions from there into the > hypervisor''s address space. > This speeds up #NPF intercepts quite a lot and avoids cache and TLB > trashing.This is a bit skanky. I''ll have a think about a neater way of doing it. -- Keir> Signed-off-by: Andre Przywara <andre.przywara@amd.com> > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xensource.com > http://lists.xensource.com/xen-devel_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Keir Fraser
2011-Apr-18 12:37 UTC
Re: [Xen-devel] [PATCH 3/5] svm: implement instruction fetch part of DecodeAssist
On 15/04/2011 13:22, "Andre Przywara" <andre.przywara@amd.com> wrote:> Newer SVM implementations (Bulldozer) copy up to 15 bytes from the > instruction stream into the VMCB when a #PF or #NPF exception is > intercepted. This patch makes use of this information if available. > This saves us from a) traversing the guest''s page tables, b) mapping > the guest''s memory and c) copy the instructions from there into the > hypervisor''s address space. > This speeds up #NPF intercepts quite a lot and avoids cache and TLB > trashing.Rewritten quite a bit and applied as c/s 23238. You probably should check it still works and with the performance improvement you expect. :-) -- Keir> Signed-off-by: Andre Przywara <andre.przywara@amd.com> > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xensource.com > http://lists.xensource.com/xen-devel_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel