Xen devel - Oct 2010 - [PATCH 05/13] Nested Virtualization: CRn & paged real mode

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---to satisfy European Law for business letters:
Advanced Micro Devices GmbH
Einsteinring 24, 85609 Dornach b. Muenchen
Geschaeftsfuehrer: Alberto Bozzo, Andrew Bowd
Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen
Registergericht Muenchen, HRB Nr. 43632


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-- 
---to satisfy European Law for business letters:
Advanced Micro Devices GmbH
Einsteinring 24, 85609 Dornach b. Muenchen
Geschaeftsfuehrer: Alberto Bozzo, Andrew Bowd
Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen
Registergericht Muenchen, HRB Nr. 43632


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At 18:42 +0000 on 12 Nov (1289587334), Christoph Egger
wrote:
> @@ -1096,7 +1097,8 @@ int hvm_set_cr0(unsigned long value)
>      /* ET is reserved and should be always be 1. */
>      value |= X86_CR0_ET;
>  
> -    if ( (value & (X86_CR0_PE | X86_CR0_PG)) == X86_CR0_PG )
> +    if ( !nestedhvm_vmswitch_in_progress(v) &&
> +         (value & (X86_CR0_PE | X86_CR0_PG)) == X86_CR0_PG )
>          goto gpf;
>  
>      if ( (value & X86_CR0_PG) && !(old_value & X86_CR0_PG)
)
> @@ -1150,7 +1152,7 @@ int hvm_set_cr0(unsigned long value)
>          }
>      }
>  
> -    if ( has_arch_mmios(v->domain) )
> +    if ( !nestedhvm_vmswitch_in_progress(v) &&
has_arch_mmios(v->domain) )
>      {
>          if ( (value & X86_CR0_CD) && !(value & X86_CR0_NW)
)
>          {
Like I said last time:

I don''t think that needs to happen -- it''s up to the L1 VMM to
decide
whether the L2 VMM should be allowed to set cache control bits in CR0.

Cheers,

Tim.


-- 
Tim Deegan <Tim.Deegan@citrix.com>
Principal Software Engineer, Xen Platform Team
Citrix Systems UK Ltd.  (Company #02937203, SL9 0BG)

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On Tuesday 16 November 2010 14:19:14 Tim Deegan wrote:
> At 18:42 +0000 on 12 Nov (1289587334), Christoph Egger wrote:
> > @@ -1096,7 +1097,8 @@ int hvm_set_cr0(unsigned long value)
> >      /* ET is reserved and should be always be 1. */
> >      value |= X86_CR0_ET;
> >
> > -    if ( (value & (X86_CR0_PE | X86_CR0_PG)) == X86_CR0_PG )
> > +    if ( !nestedhvm_vmswitch_in_progress(v) &&
> > +         (value & (X86_CR0_PE | X86_CR0_PG)) == X86_CR0_PG )
> >          goto gpf;
> >
> >      if ( (value & X86_CR0_PG) && !(old_value &
X86_CR0_PG) )
> > @@ -1150,7 +1152,7 @@ int hvm_set_cr0(unsigned long value)
> >          }
> >      }
> >
> > -    if ( has_arch_mmios(v->domain) )
> > +    if ( !nestedhvm_vmswitch_in_progress(v) &&
has_arch_mmios(v->domain)
> > ) {
> >          if ( (value & X86_CR0_CD) && !(value &
X86_CR0_NW) )
> >          {
>
> Like I said last time:
>
> I don''t think that needs to happen -- it''s up to the L1
VMM to decide
> whether the L2 VMM should be allowed to set cache control bits in CR0.
I think, I misunderstood you then. Fixed in local tree.

Christoph


-- 
---to satisfy European Law for business letters:
Advanced Micro Devices GmbH
Einsteinring 24, 85609 Dornach b. Muenchen
Geschaeftsfuehrer: Alberto Bozzo, Andrew Bowd
Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen
Registergericht Muenchen, HRB Nr. 43632


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