Jan Beulich
2010-Oct-07 10:31 UTC
[Xen-devel] [PATCH] x86: emulate MSR_IA32_UCODE_REV Intel access protocol
Intel requires a write of zeros (hence such writes now get silently
ignored) followed by a cpuid(1) followed by the actual read.
Includes some code redundancy elimination possible after the actual
change.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2277,6 +2277,14 @@ static int emulate_privileged_op(struct
if ( wrmsr_safe(MSR_FAM10H_MMIO_CONF_BASE, msr_content) != 0 )
goto fail;
break;
+ case MSR_IA32_UCODE_REV:
+ if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL )
+ goto fail;
+ if ( rdmsr_safe(regs->ecx, val) )
+ goto fail;
+ if ( msr_content )
+ goto invalid;
+ break;
case MSR_IA32_MISC_ENABLE:
if ( rdmsr_safe(regs->ecx, val) )
goto invalid;
@@ -2383,11 +2391,16 @@ static int emulate_privileged_op(struct
regs->eax = regs->edx = 0;
break;
}
- if ( rdmsr_safe(regs->ecx, msr_content) != 0 )
- goto fail;
- regs->eax = (uint32_t)msr_content;
- regs->edx = (uint32_t)(msr_content >> 32);
- break;
+ goto rdmsr_normal;
+ case MSR_IA32_UCODE_REV:
+ BUILD_BUG_ON(MSR_IA32_UCODE_REV != MSR_AMD_PATCHLEVEL);
+ if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+ {
+ if ( wrmsr_safe(MSR_IA32_UCODE_REV, 0) )
+ goto fail;
+ sync_core();
+ }
+ goto rdmsr_normal;
case MSR_IA32_MISC_ENABLE:
if ( rdmsr_safe(regs->ecx, msr_content) )
goto fail;
@@ -2395,8 +2408,6 @@ static int emulate_privileged_op(struct
regs->eax = (uint32_t)msr_content;
regs->edx = (uint32_t)(msr_content >> 32);
break;
- case MSR_EFER:
- case MSR_AMD_PATCHLEVEL:
default:
if ( rdmsr_hypervisor_regs(regs->ecx, &val) )
{
@@ -2412,6 +2423,8 @@ static int emulate_privileged_op(struct
if ( rc )
goto rdmsr_writeback;
+ case MSR_EFER:
+ rdmsr_normal:
/* Everyone can read the MSR space. */
/* gdprintk(XENLOG_WARNING,"Domain attempted RDMSR
%p.\n",
_p(regs->ecx));*/
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