Xen devel - Jun 2010 - Fix bug in VMX VPMU fixed function PMC offset

This is a minor fix to the calculation of bit-width of fixed function perfmon
counters in Intel processors.
Bits 5-12 of edx register should be calculated as (edx & 0x1fe0) >>5
instead of using 0x1f70.


diff -r b9c541d9c138 xen/arch/x86/hvm/vmx/vpmu_core2.c
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c Tue Jun 15 13:27:14 2010 +0100
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c Mon Jun 21 10:54:39 2010 +0530
@@ -83,7 +83,7 @@
 {
     u32 eax, ebx, ecx, edx;
     cpuid(0xa, &eax, &ebx, &ecx, &edx);
-    return ((edx & 0x1f70) >> 5);
+    return ((edx & 0x1fe0) >> 5);
 }

 static int is_core2_vpmu_msr(u32 msr_index, int *type, int *index)



 Thanks,
 Jaiber


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel