Hi, This patch is a workaround of AMD erratum 411 for family 10h CPUs. This does not cause functional issues but may reduce the power saving effectiveness of message-triggered C1e mode. This would normally occur only if OS which has used the local APIC timer masks the interrupt without clearing Timer Initial Count Register. Thanks, Wei Signed-off-by: Wei Wang <wei.wang2@amd.com> -- AMD GmbH, Germany Operating System Research Center Legal Information: Advanced Micro Devices GmbH Karl-Hammerschmidt-Str. 34 85609 Dornach b. München Geschäftsführer: Andrew Bowd, Thomas M. McCoy, Giuliano Meroni Sitz: Dornach, Gemeinde Aschheim, Landkreis München Registergericht München, HRB Nr. 43632 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Keir Fraser
2010-Jun-04 12:31 UTC
Re: [Xen-devel] [PATCH] A workaround for AMD erratum 411
I don''t think we are susceptible to this bug, but it''s probably a nice thing to do anyway. I will apply some variant of it to xen-unstable at least. -- Keir On 04/06/2010 12:33, "Wei Wang2" <wei.wang2@amd.com> wrote:> Hi, > This patch is a workaround of AMD erratum 411 for family 10h CPUs. This does > not cause functional issues but may reduce the power saving effectiveness of > message-triggered C1e mode. This would normally occur only if OS which has > used the local APIC timer masks the interrupt without clearing Timer Initial > Count Register. > > Thanks, > Wei > > Signed-off-by: Wei Wang <wei.wang2@amd.com>_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel