Mark Langsdorf
2010-May-14 19:19 UTC
[Xen-devel] [PATCH] Add MSR support for new AMD processor families
# HG changeset patch
# User mark.langsdorf@amd.com
# Date 1273864331 18000
# Node ID 4a31a88f1116cb77e1a3e532341a14f6560e3b0b
# Parent baccadfd9418b8dee931945e5752cb118f5bf3cb
Add MSR support for various feature AMD processor families.
Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
diff -r baccadfd9418 -r 4a31a88f1116 xen/arch/x86/apic.c
--- a/xen/arch/x86/apic.c Fri May 14 08:05:05 2010 +0100
+++ b/xen/arch/x86/apic.c Fri May 14 14:12:11 2010 -0500
@@ -823,7 +823,7 @@
switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_AMD:
if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1)
||
- (boot_cpu_data.x86 >= 15 && boot_cpu_data.x86 <= 17))
+ (boot_cpu_data.x86 >= 0xf && boot_cpu_data.x86 <=
0x17))
break;
goto no_apic;
case X86_VENDOR_INTEL:
diff -r baccadfd9418 -r 4a31a88f1116 xen/arch/x86/cpu/amd.c
--- a/xen/arch/x86/cpu/amd.c Fri May 14 08:05:05 2010 +0100
+++ b/xen/arch/x86/cpu/amd.c Fri May 14 14:12:11 2010 -0500
@@ -433,10 +433,9 @@
}
switch (c->x86) {
- case 15:
+ case 0xf:
/* Use K8 tuning for Fam10h and Fam11h */
- case 0x10:
- case 0x11:
+ case 0x10 ... 0x17:
set_bit(X86_FEATURE_K8, c->x86_capability);
disable_c1e(NULL);
if (acpi_smi_cmd && (acpi_enable_value | acpi_disable_value))
@@ -500,7 +499,7 @@
#endif
/* Pointless to use MWAIT on Family10 as it does not deep sleep. */
- if (c->x86 == 0x10 && !force_mwait)
+ if (c->x86 >= 0x10 && !force_mwait)
clear_bit(X86_FEATURE_MWAIT, c->x86_capability);
/* K6s reports MCEs but don''t actually have all the MSRs */
diff -r baccadfd9418 -r 4a31a88f1116 xen/arch/x86/cpu/mcheck/mce.c
--- a/xen/arch/x86/cpu/mcheck/mce.c Fri May 14 08:05:05 2010 +0100
+++ b/xen/arch/x86/cpu/mcheck/mce.c Fri May 14 14:12:11 2010 -0500
@@ -599,8 +599,7 @@
rc = amd_k8_mcheck_init(ci);
break;
- case 0x10:
- case 0x11:
+ case 0x10 ... 0x17:
rc = amd_f10_mcheck_init(ci);
break;
}
diff -r baccadfd9418 -r 4a31a88f1116 xen/arch/x86/nmi.c
--- a/xen/arch/x86/nmi.c Fri May 14 08:05:05 2010 +0100
+++ b/xen/arch/x86/nmi.c Fri May 14 14:12:11 2010 -0500
@@ -323,7 +323,7 @@
case X86_VENDOR_AMD:
switch (boot_cpu_data.x86) {
case 6:
- case 15 ... 17:
+ case 0xf ... 0x17:
setup_k7_watchdog();
break;
default:
diff -r baccadfd9418 -r 4a31a88f1116 xen/arch/x86/oprofile/nmi_int.c
--- a/xen/arch/x86/oprofile/nmi_int.c Fri May 14 08:05:05 2010 +0100
+++ b/xen/arch/x86/oprofile/nmi_int.c Fri May 14 14:12:11 2010 -0500
@@ -451,6 +451,18 @@
model = &op_athlon_spec;
cpu_type = "x86-64/family11";
break;
+ case 0x12:
+ model = &op_athlon_spec;
+ cpu_type = "x86-64/family12";
+ break;
+ case 0x14:
+ model = &op_athlon_spec;
+ cpu_type = "x86-64/family14";
+ break;
+ case 0x15:
+ model = &op_athlon_spec;
+ cpu_type = "x86-64/family15";
+ break;
}
break;
diff -r baccadfd9418 -r 4a31a88f1116 xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c Fri May 14 08:05:05 2010 +0100
+++ b/xen/arch/x86/traps.c Fri May 14 14:12:11 2010 -0500
@@ -2246,7 +2246,7 @@
break;
case MSR_AMD64_NB_CFG:
if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
- boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x11 )
+ boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17 )
goto fail;
if ( !IS_PRIV(v->domain) )
break;
@@ -2259,7 +2259,7 @@
break;
case MSR_FAM10H_MMIO_CONF_BASE:
if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
- boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x11 )
+ boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17 )
goto fail;
if ( !IS_PRIV(v->domain) )
break;
@@ -3247,8 +3247,7 @@
switch ( boot_cpu_data.x86 )
{
case 6:
- case 15:
- case 16:
+ case 0xf ... 0x17:
this_cpu(ler_msr) = MSR_IA32_LASTINTFROMIP;
break;
}
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Jan Beulich
2010-May-17 08:32 UTC
Re: [Xen-devel] [PATCH] Add MSR support for new AMD processor families
>>> Mark Langsdorf <mark.langsdorf@amd.com> 14.05.10 21:19 >>> >@@ -500,7 +499,7 @@ > #endif > > /* Pointless to use MWAIT on Family10 as it does not deep sleep. */ >- if (c->x86 == 0x10 && !force_mwait) >+ if (c->x86 >= 0x10 && !force_mwait) > clear_bit(X86_FEATURE_MWAIT, c->x86_capability); > > /* K6s reports MCEs but don''t actually have all the MSRs */Is this indeed the right thing to do on *all* processors starting with Fam10? Jan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel