Hello all, AMD manual states about STGI instruction: "This instruction generates a #UD exception is SVM is not enabled." However, if I execute in ring-0 the STGI instruction in my system with EFER.SVME == 0, I receive a #GP exception instead of a #UD exception. In other test, I just set the SVME bit to 1 and now I receive a #UD exception! Is the manual wrong? P.S.: My CPU obviously has the SVM extensions (AMD X2 4600+ AM2) -- View this message in context: http://www.nabble.com/STGI--UD-exception-tf3949976.html#a11206287 Sent from the Xen - Dev mailing list archive at Nabble.com. _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
mythbuster wrote:> Hello all, > > AMD manual states about STGI instruction: > > "This instruction generates a #UD exception is SVM is not enabled." > > However, if I execute in ring-0 the STGI instruction in my system with > EFER.SVME == 0, I receive a #GP exception instead of a #UD exception. > In other test, I just set the SVME bit to 1 and now I receive a #UD > exception!So SVM doesn''t work at all? Have you checked to see if it''s disabled in your BIOS? Regards, Anthony Liguori> Is the manual wrong? > > P.S.: My CPU obviously has the SVM extensions (AMD X2 4600+ AM2)_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel