Xen devel - Dec 2006 - [PATCH][RFC] Implement interrupt affinity for dom0 in IPF side

Hi keir,


Until now, all interrupts of dom0 are delivered to vcpu0 of dom0.

This patch implements interrupt affinity for dom0 in IPF side.

The method is to capture the operation where dom0 programs IOSAPIC,
Thus Xen can know which interrupt of dom0 will pin to which vcpu of
dom0.

In IA32 side, dom0 programs IO-APIC RTE to logical dest mode, 
So it''s difficult for XEN to know the interrupt binding imformation of
dom0.

What''s your opinion about this?

Thanks,
Anthony


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On 30/12/06 5:08 am, "Xu, Anthony" <anthony.xu@intel.com> wrote:
> The method is to capture the operation where dom0 programs IOSAPIC,
> Thus Xen can know which interrupt of dom0 will pin to which vcpu of
> dom0.
> 
> In IA32 side, dom0 programs IO-APIC RTE to logical dest mode,
> So it''s difficult for XEN to know the interrupt binding
imformation of
> dom0.
> 
> What''s your opinion about this?
On x86 we throw away dom0''s setting of the target field of IOAPIC
routing
entries -- Xen has complete control over that field. Also, we already have a
way to specify interrupt affinity, via EVTCHNOP_bind_vcpu. PIRQ event
channels always start their life bound to VCPU0 and then this can be
immediately changed by the guest if it so wishes. This is all already hooked
into Linux''s interrupt-affinity subsystem. Given this is the model, it
doesn''t make much sense for Xen to tell the guest what the interrupt
binding
is.

*However* it is true that currently changes to PIRQ affinity are not
notified to platform code inside Xen. So the right patch would probably be
to define a platform-specific pirq_guest_bind_vcpu() or similar, called from
the EVTCHNOP_ code. Doing it properly is somewhat complicated by the fact
that VCPUs may migrate around the place: the question then is is it worth
reprogramming the IOAPIC routing entry, etc.

 -- Keir



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