similar to: Compare rows of two matrices

Hi, I am trying to create a dotplot where each panel shows levels vs. responses; the levels are sorted by responses but levels vary from one panel to another. However, I run into problems with controlling the y-limits and y-labels. In particular, suppose I have a data frame rsp <- c(10,2,4,0,2,3) lvl <-

The following IR implements the following nested loop: for (int i = start ; i < end ; ++i ) for (int p = 0 ; p < 4 ; ++p ) a[i*4+p] = b[i*4+p] + c[i*4+p]; define void @main(i64 %arg0, i64 %arg1, i1 %arg2, i64 %arg3, float* noalias %arg4, float* noalias %arg5, float* noalias %arg6) { entrypoint: br i1 %arg2, label %L0, label %L1 L0:

The loop vectorizer relies on cleanup passes to be run after it: from Transforms/IPO/PassManagerBuilder.cpp: // Add the various vectorization passes and relevant cleanup passes for // them since we are no longer in the middle of the main scalar pipeline. MPM.add(createLoopVectorizePass(DisableUnrollLoops)); MPM.add(createInstructionCombiningPass());

Excellent. That was very helpful. Now I have full control about my NA?s :-) Thank you very much!!! Matthias > > Here is an another way > > count <- is.na(x) + is.na(y) > which( count == 1, arr.ind=TRUE ) > > 'count' gives you the number of missing values at for each > row and column. Then you can find out how many occurances of > both missing,

The instcombine pass cleans up a lot. Any idea why there are still shufflevector, insertelement, *and* bitcast (!!) etc. instructions left? The original loop is so clean, a textbook example I'd say. There is no need to shuffle anything.At least I don't see it. Frank vector.ph: ; preds = %L5 %broadcast.splatinsert1 = insertelement <4 x

Hi, How does the requirement that phi instructions have one value per predecessor basic block interact with indirectbr instructions? For instance, take the following code: L1: br i1 %somevalue, label %L2, label %L3 L2: %ret1 = i8* blockaddress(@myfunction, %L5) br label %L4 L3: %ret2 = i8* blockaddress(@myfunction, %L6) br label %L4 L4: %ret = phi i8* [%ret1, L2], [%ret2, L3]

Hello all, I don't understand a strange behavior in data frame manipulation. data_frame1 = data.frame(Site = c("S1", "S2", "S3", "S4", "L1", "L2", "L3", "L4"), Number = c(1, 3, 5, 2, 1, 1, 2, 1)) data_frame2 = data_frame1 [data_frame1$Site != "S1", ] dput (data_frame2) structure(list(Site =

On 10/12/2016 3:15 PM, Alex Bradley wrote: > > Yes the result goes into memory. But the *address* of that destination > memory location also needs to be loaded first into a register. > Your architecture has a single instruction for the following operation? define void @foo(i32 **%a, i32**%b) { entry: %l1 = load i32*, i32** %a, align 4 %l2 = load i32, i32* %l1, align 4 %l3 =

I'm fitting a GLMM to some questionnaire data. The structure is J individuals, nested within I areas, all of whom answer the same K (ordinal) questions. The model I'm using is based on so-called continuation ratios, so that it can be fitted using the lme4 package. The lmer function fits the model just fine, but using mcmcsamp to judge the variability of the parameter estimates produces

Hi to all, I am trying to run breakpoints() on a fairly large sample (>10.000 observations). The process is very slow, any idea on how to speed this up? I have tried the hpc="foreach" parameter, but this didn't work at all when I tried to run it on a smaller sample. breakpoints(x ~ x.l1 + x.l2 + X.l3 + x.l4 + x.l5 + x.l6 + x.l7 + x.l8 + y.l1 + y.l2 + y.l3 + y.l4 + y.l5 + y.l6

Hi all, Recently, I read codes about the shadow page table. I''m wondering whether the kernel has provided the function to revoke write access of all the shadows of one domain. If you know one with this function, please tell me about it. Thanks. BTW, I have my own idea to implement this. My idea is as follows: void sh_revoke_write_access_all(struct domain *d) {

I have used asterisk-1.4.14, zaptel-1.4.7, chan_ss7-1.0.0 on FC7 all went okay. using sangoma a104dx on both machine. I followed the write up on http://www.voip-info.org/wiki/index.php?page=Asterisk+ss7+setup I have the cross over cable between them. however, wanpipe shows connected but the signaling link does not align. i have my configs for host A ##wanpipe1.conf [devices] wanpipe1 =

On 11/12/2009, at 10:43 AM, Anton Korobeynikov wrote: > Hi, Chris > >> That is target independent code, so you should not put sparc specific changes there. It sounds like one of the sparc-specific target hooks is wrong. > Since sparc does not provide any hooks for operation of branches (e.g. > AnalyzeBranch and friends) it might be possible that generic codegen > code is

Xen 3.2.1-rc1 64 bit Dom0: 2.6.16.33 PAE DomU: 2.6.18.8 (from a pull a few weeks ago) If you need the symbols, there from the same Xen I linked to in my post from a few days ago... (XEN) mm.c:3498:d4 ptwr_emulate: could not get_page_from_l1e() (XEN) Unhandled page fault in domain 4 on VCPU 0 (ec=0003) (XEN) Pagetable walk from 00000000c08187f0: (XEN) L4[0x000] = 00000004dfa38027

On Feb 8, 2010, at 12:37 AM, Nathan Keynes wrote: > Firstly, the BNE/BA pair should be reduced to a BE (I assume this is > the responsibility of AnalyzeBranch and friends that you mention). Right. Implementing AnalyzeBranch will allow a bunch of block layout and branch optimizations to happen. > However I still wouldn't have expected that to result in the label > being

John Ackermann N8UR via Nut-upsuser <nut-upsuser at alioth-lists.debian.net> writes: > I am monitoring via the SNMP driver an APC SmartUPS that has split > phase (2L + neutral) 240V input and 120/120 volt outputs. The data > for the voltages is not what I'm expecting, and I am wondering how I > should interpret it. Wow, that sounds kind of industrial. Model? Is the

Sounds pretty normal from what I see. It appears that this is *NOT* a true 240v UPS, but rather one that provides two legs of 120v output from two legs of 120 input, and what is seen as "L2" is actually neutral, and the line names are reporting incorrectly. With that in mind, each leg in should be 120v, as well as the outputs, which is exactly what you are seeing.(The fact tht L1 to L3

I think that's incorrect. It should to: .section .foo .L1: .L2 = .L1 .section .bar .long .L3-.L2 .L3: Because .L3 and .L2 are in different sections. - Justin On Thu, Jun 26, 2014 at 2:46 PM, Rafael Espíndola <rafael.espindola at gmail.com> wrote: > This reduces to > > .section .foo > .L1: > .L2 = .L1 > .section .bar > .long .L1-.L2 > > > Which is fairly

Thanks, Tim. The unit was available with single as well as split phase output, and from the data I can find the input was single phase, though the input connector has L1/L2/N/G wires. I'm digging through the MIB to see what the raw data looks like. Thanks! John ---- On 11/11/24 19:14, Tim Dawson wrote: > Sounds pretty normal from what I see. It appears that this is *NOT* a > true

Hi -- I am monitoring via the SNMP driver an APC SmartUPS that has split phase (2L + neutral) 240V input and 120/120 volt outputs. The data for the voltages is not what I'm expecting, and I am wondering how I should interpret it. Here is an example from upsc: input.L1-L2.voltage: 121 input.L2-L3.voltage: 120 input.voltage: 121.20 output.current: 5.90 output.L1-L2.voltage: 119