similar to: [PATCH] x86: s3: ensure CR4.MCE is enabled after mcheck_init()

Now if VT-d is enabled, when Dom0 does S3, Xen doesn''t suspend/resume the IOMMU states. The patch adds the missing invocations of iommu_suspend()/iommu_resume() and makes some nesessary fixes: 1) In iommu_set_root_entry(), we should not re-allocate the root-entry when Xen returns from S3; 2) Define the array iommu_state correctly (u8 -> u32); 3) Only save/restore the necessary IOMMU

Hi Jan Beulich, > changeset 15414: 3cf5052ba5e5 x86: machine check exception handling With the c/s, when creating HVM guest, I can only see a white Qemu window. :( Can you have a look? Thanks. PS: the serial log follows: (XEN) HVM1: pci dev 02:0 bar 14 size 00001000: f2000000 (XEN) HVM1: pci dev 03:0 bar 10 size 00000100: 0000c101 (XEN) HVM1: pci dev 03:0 bar 14 size 01000000:

Hi, all I want to reduce the checkpoint size of a VM by memory exclusion. I try to find out all the free pages by reference count at VMM-level, As they declared that: /* Page is on a free list: ((count_info & PGC_count_mask) == 0). */ , in struct page_info which is defined in /xen/include/asm-x86/mm.h, but unfortunately, all the pages in a idle VM accords with this condition.

Any advice about the patch cr8-acceleration-3.patch? Hi Keir, could you give some comments? Thanks! -- Dexuan -----Original Message----- From: xen-devel-bounces@lists.xensource.com [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Cui, Dexuan Sent: 2006年10月25日 11:12 To: Keir.Fraser@cl.cam.ac.uk Cc: xen-devel@lists.xensource.com Subject: [Xen-devel] [Patch][RESEND] Add hardware CR8

The Xen platform device (introduced in changeset 11161) would cause HCT''s PCI Compliance Test to generate a failure message. The patch fixes this. Thanks Dexuan Cui Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Dump mce log by ERST when mc panic We have implemented basic ERST logic before. Now linux3.0 as dom0 has included APEI logic. Hence it''s time to add mce apei interface and enable APEI ERST feature. With it, it can save mce log by ERST method when mc panic. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> diff -r ca2f58c2dfea xen/arch/x86/cpu/mcheck/mce.c ---

Changeset 15046:e527b4ff1948 breaks 32-bit HVM guest: when req->size is 4, "1UL << 32" returns 1 in IA32 system, so the mask becomes 0 wrongly. The attached patch fixes this by using 64-bit left-shift. Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

Sorry, please ignore this mail. (I attached the old patch...) -- Dexuan -----Original Message----- From: xen-devel-bounces@lists.xensource.com [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Cui, Dexuan Sent: 2006年10月25日 11:07 To: Keir.Fraser@cl.cam.ac.uk Cc: xen-devel@lists.xensource.com Subject: [Xen-devel] [Patch][RESEND] Add hardware CR8 acceleration for TPRaccessing x64

On platforms which supports x2APIC, the patches enable this enhancement for Xen. The x2APIC specification is available at http://www.intel.com/products/processor/manuals/ http://download.intel.com/design/processor/specupdt/318148.pdf apicid_u8_2_u32.patch: changes the ''apicid'' from u8 to u32; x2apic.patch: replaces the traditional MMIO-style interface to the MSR-style one; uses

The PCI_EXP_TYPE_PCI_BRIDGE should be PCI_EXP_FLAGS_TYPE here. Also a tiny fix to the python comment. Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

This issue I am encountering seems to only happen on multi-socket machines. It also does not help that the only multi-socket box I have is an Romley-EP (so two socket SandyBridge CPUs). The other SandyBridge boxes I''ve (one socket) are not showing this. Granted they are also a different model (42). The problem is that when I run ''perf top'' within an SMP PVHVM guest,

Some operating systems access the local APIC TPR very frequently, and we handle that using software-based local APIC virtualization in Xen today. Such virtualization incurs a number of VM exits from the memory-access instructions against the APIC page in the guest. The attached patch enables the TPR shadow feature that provides APIC TPR virtualization in hardware. Our tests indicate it can

In x64 SMP Vista HVM guest (vcpus=2 in the configuration file), the wall clock time is 50% slower than that in the real world. The attached patch fixes the issue. -- Dexuan Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

This patch initializes VMCB CR4 and shadow CR4 with 0 when VMCB is being constructed under nested paging mode. It complies with recent reset_to_realmode change in hvmloader. Signed-off-by: Wei Huang (wei.huang2@amd.com <mailto:wei.huang2@amd.com> ) _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

Thanks for your advice. I will re-organize the patch. Thanks -- Dexuan -----Original Message----- From: Li, Xin B Sent: 2006年10月24日 18:08 To: Petersson, Mats; Cui, Dexuan; Betak, Travis Cc: xen-devel@lists.xensource.com Subject: RE: [Xen-devel] [Patch] Add hardware CR8 acceleration for TPRaccessing >> From: xen-devel-bounces@lists.xensource.com >>

On Sat, Aug 29, 2020 at 05:55:25PM +0200, Borislav Petkov wrote: > On Mon, Aug 24, 2020 at 10:54:33AM +0200, Joerg Roedel wrote: > > From: Joerg Roedel <jroedel at suse.de> > > > > Early exception handling will use rd/wrgsbase in paranoid_entry/exit. > > Enable the feature to avoid #UD exceptions on boot APs. > > > > Signed-off-by: Joerg Roedel

Thank you. I notice the system then jumps to F000:FFF0 to execute. But because VMX is turned on, switching to real-mode would incur problems? I don’t find any clue to turn on the vm86 mode as Readme in the tools/firmware directory puts. Best regards, Hu Jia Yi Ext: 20430 Tel: 65-67510430 -----Original Message----- From: Cui, Dexuan [mailto:dexuan.cui@intel.com] Sent: Thursday,

On Fri, Sep 27, 2019 at 05:37:20AM +0000, Dexuan Cui wrote: > > From: linux-hyperv-owner at vger.kernel.org > > <linux-hyperv-owner at vger.kernel.org> On Behalf Of Stefano Garzarella > > Sent: Thursday, September 26, 2019 12:48 AM > > > > Hi Dexuan, > > > > On Thu, Sep 26, 2019 at 01:11:27AM +0000, Dexuan Cui wrote: > > > ... > >

I have just starting auditing the NMI path and found that the oprofile code calls into a fair amount of common code. So far, down the first leg of the call graph, I have found several ASSERT()s, a BUG() and many {rd,wr}msr()s. Given that these are common code, and sensible in their places, removing them for the sake of being on the NMI path seems silly. As an alternative, I suggest that we make

The datasheet is available at http://download.intel.com/design/network/datashts/82599_datasheet.pdf See 'Table 9.7. VF PCIe Configuration Space' of the datasheet, the PCI Express Capability Structure of the VF of Intel 82599 10GbE Controller looks trivial, e.g., the PCI Express Capabilities Register is 0, so the Capability Version is 0 and pt_pcie_size_init() would fail. We should not