similar to: [PATCH] A fix for CR8 acceleration on 64bit guest

This patch adds CR8 virtualization. It''s the initial patch for booting HVM x64 Windows guest, and just let every CR8 access issues vmexit. And later we will do acceleration to it. Signed-off-by: Xiaohui Xin <xiaohui.xin@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Thanks for your advice. I will re-organize the patch. Thanks -- Dexuan -----Original Message----- From: Li, Xin B Sent: 2006年10月24日 18:08 To: Petersson, Mats; Cui, Dexuan; Betak, Travis Cc: xen-devel@lists.xensource.com Subject: RE: [Xen-devel] [Patch] Add hardware CR8 acceleration for TPRaccessing >> From: xen-devel-bounces@lists.xensource.com >>

Any advice about the patch cr8-acceleration-3.patch? Hi Keir, could you give some comments? Thanks! -- Dexuan -----Original Message----- From: xen-devel-bounces@lists.xensource.com [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Cui, Dexuan Sent: 2006年10月25日 11:12 To: Keir.Fraser@cl.cam.ac.uk Cc: xen-devel@lists.xensource.com Subject: [Xen-devel] [Patch][RESEND] Add hardware CR8

Sorry, please ignore this mail. (I attached the old patch...) -- Dexuan -----Original Message----- From: xen-devel-bounces@lists.xensource.com [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Cui, Dexuan Sent: 2006年10月25日 11:07 To: Keir.Fraser@cl.cam.ac.uk Cc: xen-devel@lists.xensource.com Subject: [Xen-devel] [Patch][RESEND] Add hardware CR8 acceleration for TPRaccessing x64

TPR shadow/threshold feature is important to speedup the boot time for Windows guest. Besides, it is a must feature for certain VMM. We map virtual APIC page address and TPR threshold from L1 VMCS, and synch it into shadow VMCS in virtual vmentry. If TPR_BELOW_THRESHOLD VM exit is triggered by L2 guest, we inject it into L1 VMM for handling. Besides, this commit fixes an issue for apic access

[VMX] Add support for Pause-Loop Exiting New NHM processors will support Pause-Loop Exiting by adding 2 VM-execution control fields: PLE_Gap - upper bound on the amount of time between two successive executions of PAUSE in a loop. PLE_Window - upper bound on the amount of time a guest is allowed to execute in a PAUSE loop If the time, between this execution of PAUSE

On Mon, Jul 15, 2019 at 4:30 PM Andrew Cooper <andrew.cooper3 at citrix.com> wrote: > > On 15/07/2019 19:17, Nadav Amit wrote: > >> On Jul 15, 2019, at 8:16 AM, Andrew Cooper <andrew.cooper3 at citrix.com> wrote: > >> > >> There is a lot of infrastructure for functionality which is used > >> exclusively in __{save,restore}_processor_state() on

On 15/07/2019 19:17, Nadav Amit wrote: >> On Jul 15, 2019, at 8:16 AM, Andrew Cooper <andrew.cooper3 at citrix.com> wrote: >> >> There is a lot of infrastructure for functionality which is used >> exclusively in __{save,restore}_processor_state() on the suspend/resume >> path. >> >> cr8 is an alias of APIC_TASKPRI, and APIC_TASKPRI is saved/restored

On 15/07/2019 19:17, Nadav Amit wrote: >> On Jul 15, 2019, at 8:16 AM, Andrew Cooper <andrew.cooper3 at citrix.com> wrote: >> >> There is a lot of infrastructure for functionality which is used >> exclusively in __{save,restore}_processor_state() on the suspend/resume >> path. >> >> cr8 is an alias of APIC_TASKPRI, and APIC_TASKPRI is saved/restored

> On Jul 15, 2019, at 8:16 AM, Andrew Cooper <andrew.cooper3 at citrix.com> wrote: > > There is a lot of infrastructure for functionality which is used > exclusively in __{save,restore}_processor_state() on the suspend/resume > path. > > cr8 is an alias of APIC_TASKPRI, and APIC_TASKPRI is saved/restored by > lapic_{suspend,resume}(). Saving and restoring cr8

There is a lot of infrastructure for functionality which is used exclusively in __{save,restore}_processor_state() on the suspend/resume path. cr8 is an alias of APIC_TASKPRI, and APIC_TASKPRI is saved/restored by lapic_{suspend,resume}(). Saving and restoring cr8 independently of the rest of the Local APIC state isn't a clever thing to be doing. Delete the suspend/resume cr8 handling,

There is a lot of infrastructure for functionality which is used exclusively in __{save,restore}_processor_state() on the suspend/resume path. cr8 is an alias of APIC_TASKPRI, and APIC_TASKPRI is saved/restored by lapic_{suspend,resume}(). Saving and restoring cr8 independently of the rest of the Local APIC state isn't a clever thing to be doing. Delete the suspend/resume cr8 handling,

There is a lot of infrastructure for functionality which is used exclusively in __{save,restore}_processor_state() on the suspend/resume path. cr8 is an alias of APIC_TASKPRI, and APIC_TASKPRI is saved/restored independently by lapic_{suspend,resume}(). Delete the saving and restoration of cr8, which allows for the removal of both PVOPS. Signed-off-by: Andrew Cooper <andrew.cooper3 at

There is a lot of infrastructure for functionality which is used exclusively in __{save,restore}_processor_state() on the suspend/resume path. cr8 is an alias of APIC_TASKPRI, and APIC_TASKPRI is saved/restored independently by lapic_{suspend,resume}(). Delete the saving and restoration of cr8, which allows for the removal of both PVOPS. Signed-off-by: Andrew Cooper <andrew.cooper3 at

My recent interest in the TPR-write problem has got me thinking about if there is any other optimisation that could be done for windows, especially as a few people have reported issues with more than a few processors, and they say they are already running 2K3sp2 which should have TPR optimisation in it already. Is there any facility currently for profiling the frequency of vmexit''s to

Change from v2: re-written code in ''vmx_intr_assist'' into if()/else if() sequence to make code change easy to review. Virtual interrupt delivery avoids Xen to inject vAPIC interrupts manually, which is fully taken care of by the hardware. This needs some special awareness into existing interrupr injection path: For pending interrupt from vLAPIC, instead of direct injection, we

The patch enables x86_32 PAE unmodified guests on 64-bit Xen when the hvm feature is present. We tested only Linux at this point, and we''ll improve the functionality as we test other guests. The SVM needs the equivalent changes to the vmc.c to get this functionality working, but this patch does not break the build. Signed-off-by: Jun Nakajima <jun.nakajima@intel.com>

From: Nicu?or C??u <ncitu at bitdefender.com> This function is needed for the KVMI_VCPU_INJECT_EXCEPTION command. Signed-off-by: Nicu?or C??u <ncitu at bitdefender.com> Signed-off-by: Adalbert Laz?r <alazar at bitdefender.com> --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/x86.c | 71 ++++++++++++++++++--------------- 2 files changed, 39 insertions(+),

The patch attached is to set effective memory type for EPT according to the VT-d snoop control capability, and also includes some cleansup for EPT & VT-d both enabled. Signed-off-by: Zhai, Edwin Edwin.Zhai@intel.com<mailto:Edwin.Zhai@intel.com> Signed-off-by: Xin, Xiaohui xiaohui.xin@intel.com<mailto:xiaohui.xin@intel.com> _______________________________________________

Ian, Keir, This patch is to boot 32-bit VMX guest on the 64-bit host. Double-compile is used to make both 64-bit guest and 32-bit guest can work, the shadow page-table uses current 64-bit shadow code''s structure to simulate 32-bit guest''s 2-level page-table. Signed-off-by: Chengyuan Li <chengyuan.li@intel.com> Signed-off-by: Xiaohui Xin <xiaohui.xin@intel.com>