similar to: [PATCH]vtd, one more fix about PMR disable

HPET intr-near-missing means if the current counter value is too close to the comparator value to be reprogrammed the expected HPET intr may be missing. Linux kernel uses a mininal 48-hpet-ticks(~3.5us) distance to workaround this, but personal observation showed there is still failure case while delta=0xba (~13.5us). So choosing 20us as the MIN_DELTA_NS should be helpful to prevent near-missing

Local APIC timer may stop at deep C state (C3/C4...) entry/exit. Initial HPET broadcast working in legacy replacing mode, broke RTC intr, so was bypassed. This patch add the logic that use platform timer (PIT) to reenable local APIC timer at C state entry/exit. Currently, only keep PIT enabled with 100Hz freq. The next step is trying to dynamically enable/disable PIT while needed, and give it

The iommu is enabled by default when xen is booting and later disabled in iommu_setup() when no iommu is present. But under some circumstances iommu code can be called before iommu_setup() is processed. If there is no iommu available xen crashes. This can happen for example when panic(...) is called as introduced with the patch "x86-64: detect processors subject to AMD erratum #121 and

Attached is a patch for shared interrupt between dom0 and HVM domain for vtd. Most of problem is caused by that we should inject interrupt to both domains and the physical interrupt deassertion then may be delayed by the device assigned to the HVM. The patch adds a timer, and the time out value is sufficient large to tolerant the delaying used to wait for the physical interrupt deassertion.

Keir, It''s a resending patch for the timeout mechanism to deal with the shared interrupt issue for vt-d enabled hvm guest. We modify the patch following your comments last time and make some other small fix: 1) We don''t touch the locking around the hvm_dpci_eoi(). 2) Remove the HZ from the TIME_OUT_PERIOD macro which may confuse others. 3) Add some

Add TSC stop support for Deep C state TSC may stop at deep C state (C3/C4...) entry/exit. this patch add the logic that save and restore TSC during deep C state entry/exit, by using platform timer (PIT/HPET) signed-off-by: Yu Ke <ke.yu@intel.com> signed-off-by: Tian Kevin <kevin.tian@intel.com> signed-off-by: Wei Gang<gang.wei@intel.com>

CPUIDLE: Avoid remnant LAPIC timer intr while force hpetbroadcast LAPIC will stop during C3, and resume to work after exit from C3. Considering below case: The LAPIC timer was programmed to expire after 1000us, but CPU enter C3 after 100us and exit C3 at 9xxus. 0us: reprogram_timer(1000us) 100us: entry C3, LAPIC timer stop 9xxus: exit C3 due to unexpected event, LAPIC timer continue running

The iommu is enabled by default when xen is booting and later disabled in iommu_setup() when no iommu is present. But under some circumstances iommu-code can be called before iommu_setup() is processed. If there is no iommu available xen crashes. This can happen for example when panic(...) is called that got introduced with patch "x86-64: detect processors subject to AMD erratum #121 and

Current xen-linux (2.6.18) not include support for Cx MWAIT entry method. Back port from latest Linux kernel (already there since 2.6.23). Without this patch, _CST method couldn''t get C states with FFH address space type. Signed-off-by: Wei Gang <gang.wei@intel.com> Jimmy _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

cpuidle: Fix for timer_deadline==0 case After the scheduler timer became suspended before entering cpu idle state, the percpu timer_deadline is possible to be 0, i.e. no soft timer in the queue. This case will cause unexpected large residency percentage in C1 for the purely idle cpu. The fix is if timer_deadline == 0, skip most hpet broadcast enter logic because no broadcast is needed for this

The following 5 patches are re-submissions of the vt-d patch. This set of patches has been tested against cs# 15080 and is now much more mature and tested against more environments than the original patch. Specifically, we have successfully tested the patch with following environements: - 32/64-bit Linux HVM guest - 32-bit Windows XP/Vista (64-bit should work but did not test) -

Enable Px/Cx related CPUID/MSR bits for dom0 to get correct Px/Cx info. Signed-off-by: Wei Gang <gang.wei@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

The new sboot module that performs the measured launch, for Intel(R) TXT support. Part c - use ''cat'' to concatenate the pieces Signed-off-by: Joseph Cihula <joseph.cihula@intel.com> Signed-off-by: Jimmy Wei <gang.wei@intel.com> Signed-off-by: Shane Wang <shane.wang@intel.com> Signed-off-by: Zhai Edwin <edwin.zhai@intel.com>

Enable THERM_CONTROL MSR write for dom0 even cpufreq=xen Signed-off-by: Wei Gang <gang.wei@intel.com> diff -r bd683e0397b4 xen/arch/x86/traps.c --- a/xen/arch/x86/traps.c Tue Feb 17 22:29:38 2009 +0800 +++ b/xen/arch/x86/traps.c Wed Feb 25 11:23:01 2009 +0800 @@ -2187,10 +2187,17 @@ static int emulate_privileged_op(struct case MSR_IA32_MPERF: case MSR_IA32_APERF:

On Thu, 30 Sep 2010 14:02:34 +0800, gang.wei@intel.com wrote: > I am the original developer of HPET broadcast code. > > First of all, to disable HPET broadcast, no additional patch is required. > Please simply add option "cpuidle=off" or "max_cstate=1" at xen cmdline in > /boot/grub/grub.conf. > > Second, I noticed that the issue just occur on

Fix addr_to_dma_page() issue to return l1e correctly, and also clean up rmrr mapping code, make sure setup rmrr identify mapping just once per domain. This patch fixes the VT-d bug (Fail to boot smp Linux guest with VT-d NIC assigned on IA32e platform). Signed-off-by: Weidong Han <weidong.han@intel.com> _______________________________________________ Xen-devel mailing list

http://www.intel.com/content/www/us/en/chipsets/5520-and-5500-chipset-ioh-specification-update.html Stepping B-3 has two errata (#47 and #53) related to Interrupt remapping, to which the workaround is for the BIOS to completely disable interrupt remapping. These errata are fixed in stepping C-2. Unfortunately this chipset is very common and many BIOSes are not disabling remapping. We can

Local APIC timer may stop at deep C state (C3/C4...) entry/exit. this patch add the logic that use platform timer (HPET) to reenable local APIC timer at C state entry/exit. Signed-off-by: Wei Gang <gang.wei@intel.com> Signed-off-by: Yu Ke <ke.yu@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

Hi, I am having great difficulties in getting pci passthrough with VTd to work, surely I am doing something stupid but I cannot see what. "tangram" (https://www.blogger.com/profile/06588030231546523539) has been a huge help, but despite his efforts I am still stuck. Hardware: Intel S3200SHV motherboard BIOS : S3200X38.86B.00.00.0052 CPU : Intel Core 2

Now if VT-d is enabled, when Dom0 does S3, Xen doesn''t suspend/resume the IOMMU states. The patch adds the missing invocations of iommu_suspend()/iommu_resume() and makes some nesessary fixes: 1) In iommu_set_root_entry(), we should not re-allocate the root-entry when Xen returns from S3; 2) Define the array iommu_state correctly (u8 -> u32); 3) Only save/restore the necessary IOMMU