similar to: [PATCH] x86/hvm: miscellaneous CPUID handling changes

(Applies cleanly only on top of the previously sent SVM/LBR patch.) Signed-off-by: Jan Beulich <jbeulich@novell.com> Index: 2007-08-08/xen/arch/x86/hvm/svm/svm.c =================================================================== --- 2007-08-08.orig/xen/arch/x86/hvm/svm/svm.c 2007-08-08 11:40:11.000000000 +0200 +++ 2007-08-08/xen/arch/x86/hvm/svm/svm.c 2007-08-08 11:43:53.000000000 +0200

X86: Prepare PCID/INVPCID for hvm This patch is used to prepare exposing PCID/INVPCID features to hvm guest. The specific exposure result depend on hvm paging mode (hap/shadow), which would be handled at next patch. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> diff -r 1b62d4e08880 tools/libxc/xc_cpuid_x86.c --- a/tools/libxc/xc_cpuid_x86.c Thu Nov 17 23:09:45 2011 +0800 +++

Expose tsc adjust to hvm guest Intel latest SDM (17.13.3) release a new MSR CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported. This patch expose it to hvm guest. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> diff -r a6d12a1bc758 tools/libxc/xc_cpufeature.h --- a/tools/libxc/xc_cpufeature.h Thu Sep 20 00:03:25 2012 +0800 +++ b/tools/libxc/xc_cpufeature.h Thu Sep 20

Hi, I just added 32GB memory in my system and wanted Xen to see that memory, so enabled PAE in xen0 and XenU. I did a make menuconfig in xen0 and xenU, then did a make in xen-unstable and a make install. Whilebooting this kernel, I get the above error PAE mode mismatch. I looked under xen/include/asm-x86/processor.h has #define X86_CR4_PAE defined and so does cpufeature.h have this defined.

See http://lkml.org/lkml/2008/10/1/246 for more context. Signed-off-by: Jan Beulich <jbeulich@novell.com> Index: 2008-10-27/xen/arch/x86/domain.c =================================================================== --- 2008-10-27.orig/xen/arch/x86/domain.c 2008-11-11 16:24:48.000000000 +0100 +++ 2008-10-27/xen/arch/x86/domain.c 2008-11-19 10:22:34.000000000 +0100 @@ -1888,6 +1888,8 @@ void

X86: expose HLE/RTM features to dom0 Intel recently release 2 new features, HLE and TRM. Refer to http://software.intel.com/file/41417. This patch expose them to dom0. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> diff -r 92e03310878f xen/arch/x86/traps.c --- a/xen/arch/x86/traps.c Wed Feb 08 21:05:52 2012 +0800 +++ b/xen/arch/x86/traps.c Mon Feb 27 02:23:42 2012 +0800 @@ -857,9

From: Tom Lendacky <thomas.lendacky at amd.com> Add CPU feature detection for Secure Encrypted Virtualization with Encrypted State. This feature enhances SEV by also encrypting the guest register state, making it in-accessible to the hypervisor. Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com> Signed-off-by: Joerg Roedel <jroedel at suse.de> ---

CPUID level 0x00000007:0 (ebx) is word 9, instead of word 7. ... make it consistent with native Linux. Signed-off-by: Li Xin <xin.li@intel.com> diff -r d7c755c25bb9 xen/include/asm-x86/cpufeature.h --- a/xen/include/asm-x86/cpufeature.h Sat May 28 08:58:08 2011 +0100 +++ b/xen/include/asm-x86/cpufeature.h Tue May 31 07:34:34 2011 +0800 @@ -142,7 +142,7 @@ #define X86_FEATURE_TOPOEXT

Heya I made 2 torrents one is to paste in the virtual c drive, it has all the windows xp .dlls so copy all the files (one in folders will have to be done by opening folder and copying into the folder now copy and paste system 32 folder) it should increase compatability: http://extratorrent.com/torrent/2346325/System+32+.Dlls.html Please Seed CS5 .DLLs needed to run adobe Cs5:

I have searched around the lists and Google and found this HYPERLINK "http://people.freebsd.org/~pjd/patches/jail_2004120901.patch"http://people. freebsd.org/~pjd/patches/jail_2004120901.patch I was wondering if anyone know of a multiple IP patch that works with FreeBSD 5.4 I really do not understand why this is not included in the standard jail I mean sure jail is handy for

I thought I would take this opportunity to let you know what I''m doing wi= th=20 Shorewall and to start the ball rolling with this mailing list. While I continue to provide minor bug fixes and enhancements, my major ef= fort=20 is going into a GUI for Shorewall. Since I have spent the last 32+ years=20 doing kernel and middleware development, I''ve not built a GUI before.

Hi, I've been slowly but steadily working towards enabling the Mach-O/PPC backend for MC, starting with the mach-o relocation entry translation. patches/logs: http://www.csl.cornell.edu/~fang/sw/llvm/ git: http://github.com/fangism/llvm/tree/powerpc-darwin8 git: http://github.com/fangism/clang/tree/powerpc-darwin8 I've managed to get the simplest single-function-call hello-world

From: Tom Lendacky <thomas.lendacky at amd.com> Add CPU feature detection for Secure Encrypted Virtualization with Encrypted State. This feature enhances SEV by also encrypting the guest register state, making it in-accessible to the hypervisor. Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com> Signed-off-by: Joerg Roedel <jroedel at suse.de> ---

I see the problem. Let me try to come up with a solution that does not involve constructors but also does not sacrifice type safety. On Tue, Feb 7, 2012 at 12:01 PM, Chris Lattner <clattner at apple.com> wrote: > Hi Kostya, > > One unexpected piece of fallout in your recent attributes change (r148553) > was that it introduced a bunch of static constructors into .o files that

Greetings to one and all on this fine list; We have the current system: Meridian 1 Option 11 +-------------------+ | | ISDN/30 (DASS/2) ===> |NTAK79BB (2MB Pri) | | |<-->4x16 port Digital / 1x16 port Analogue ISDN/30 (EUROIDSN) ===> |NTBK50AA (2MB Pri)

Hi Kostya, One unexpected piece of fallout in your recent attributes change (r148553) was that it introduced a bunch of static constructors into .o files that #include Attributes.h, due to stuff like this: const Attributes None (0); ///< No attributes have been set const Attributes ZExt (1<<0); ///< Zero extended before/after call const Attributes SExt

[PATCH 6/8] HVM save restore: guest memory handling Signed-off-by: Zhai Edwin <edwin.zhai@intel.com> add support for save/restore HVM guest memory diff -r bb1c450b2739 tools/libxc/xc_hvm_restore.c --- a/tools/libxc/xc_hvm_restore.c Thu Jan 11 21:03:11 2007 +0800 +++ b/tools/libxc/xc_hvm_restore.c Thu Jan 11 21:05:45 2007 +0800 @@ -31,6 +31,40 @@ #include <xen/hvm/ioreq.h>

Hi, We are using samba 4.4.5, and we detected two issue, and we are not sure if both errors are related... 1) memory leak I have detected that It seems that samba 4.4.5 (AD mode) has a memory leak, because after some time memory usage is very high, for example with an environment with 150 users and Samba server with 2GB RAM after 222 days up, is using swap, and memory is increasing

MTRR is not available for PVH Dom0, so prevent cpuid from reporting it as an available feature. Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Cc: George Dunlap <george.dunlap@eu.citrix.com> Cc: Mukesh Rathor <mukesh.rathor@oracle.com> Cc: Jan Beulich <JBeulich@suse.com> Cc: Keir Fraser <keir@xen.org> --- This should go in after Mukesh Dom0 series, or merged

Hi Jan, I was wondering if we should not let the code fall through and clear all registers to zero but rather clear just the one bit we care about? My concern is that a future Intel revision may expand this function and return other information besides that XSAVEOPT, which would then be wiped out by the fall-through code. I''m thinking something like this. Let me know if I have