similar to: [Patch][RFC] Super Page Patch

Attached are the patches to support super page with EPT. We only support 2M size. And shadow may still work fine with 4K pages. The patches can be split into 3 parts. Apply order is as attached. tool.diff To allocate 2M physical contiguous memory in guest except the first 2M and the last 2M. The first 2M covers special memory, and Xen use the last few pages in guest memory to do special

This patch changes hap parameter from boolean to integer. So users can disable and enable hap using "hap=0" and "hap=1". It also prints out nested paging message under SVM. Signed-off-by: Wei Huang <wei.huang2@amd.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Also, correct a copy&paste error in the documentation. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> --- This patch has been in the XenServer patch queue for a long time. It is more for debugging purposes than anything else, but is still proving to be valuable for tracking down bugs with HVM paging operations. diff -r 5af4f2ab06f3 -r e6ec5b2b717f

This patch initializes VMCB CR4 and shadow CR4 with 0 when VMCB is being constructed under nested paging mode. It complies with recent reset_to_realmode change in hvmloader. Signed-off-by: Wei Huang (wei.huang2@amd.com <mailto:wei.huang2@amd.com> ) _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

In p2m.c (line 197 and line 550), the code assumes the number of L3 P2M table entries is 8 (under PAE mode). According to Intel and AMD specs, it is 4. Could someone explain this discrepancy? Is it a bug? -Wei _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

I''m trying to get ceph working with decent performance (currently getting kb/second write performance!) and it seems that maybe the Debian wheezy kernel is just a bit too ancient. The 3.8 kernel from experimental works on bare metal, but when booting as dom0 under the xen hypervisor it crashes. I just figured out how to redirect xen output to my IPMI/BMC serial port and I see this:

Hi Ian, There have been a lot of interest on gfx passthru recently. This patch enables ATI VBIOS in passthru mode. The guest VM system BIOS (including Windows boot logo) can now show in passthru screen. We have tested with various Windows and Linux guest VMs. Please help review it. We are also looking forward to comments and suggestions from Xen community users. Signed-off-by: Wei Huang

I am adding interrupt support for LWP, whose spec is available at http://support.amd.com/us/Processor_TechDocs/43724.pdf. Basically OS can specify an interrupt vector in LWP_CFG MSR; the interrupt will be triggered when event buffer overflows. For HVM guests, I want to re-inject this interrupt back into the guest VM. Here is one idea similar to virtualized PMU: It first registers a special

The attached patch fixes the save/restore issue seen with 32bit Windows guest VMs. The root cause is that current Xen doesn''t intercept SYSENTER-related MSRs for 32bit guest VMs. As a result, the guest_sysenter_xxx fields contain incorrect values and shouldn''t be used for save/restore. This patch checks the LMA bit of EFER register in the save/restore code path. Please apply it

The memory permutation cause a slow down in case of a save/restore (bug 1143). It works better when the mixing is done with 2MB chunks. Signed-off-by: Jean Guyader <jean.guyader@eu.citrix.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Hi, Attached patch implements the VMCB cleanbits SVM feature. Upcoming AMD CPUs introduce them and they are basically hints for the CPU which vmcb values can be re-used from the previous VMRUN instruction. Each bit represents a certain set of fields in the VMCB. Setting a bit tells the cpu it can re-use the cached value from the previous VMRUN. Clearing a bit tells the cpu to reload the values

Hi, I have installed Xen on Linux 2.6.11.10 <http://2.6.11.10> and i am trying to do Asynchronous Direct IO on SAS drives. The application which does the asynchronous direct io on SAS drive is running on Domain 0. Actually the IOPs what i get for a 512Bytes IO size is 67, but if i do the same operation on Linux 2.6.11.10 <http://2.6.11.10> native kernel, i get 267 IOPs.Cananyone

Good news/bad news testing the new kernel on CentOS7 with my now notoriously finicky machines: Good news: 4.9.23-26.el7 (grabbed today via yum update) isn't any worse than 4.9.13-22 was on my xen hosts (as far as I can tell so far at least) Bad news: It isn't any better than 4.9.13 was for me either, if I don't set vcpu limit in the grub/xen config, it still panics like so: [

Future AMD SVM supports a new feature called flush by ASID. The idea is to allow CPU to flush TLBs associated with the ASID assigned to guest VM. So hypervisor doesn''t have to reassign a new ASID in order to flush guest''s VCPU. Please review it. Thanks, Wei Signed-off-by: Wei Huang <wei.huang2@amd.com> Signed-off-by: Wei Wang <wei.wang2@amd.com> -- Advanced Micro

On 04/19/2017 12:18 PM, PJ Welsh wrote: > > On Wed, Apr 19, 2017 at 5:40 AM, Johnny Hughes <johnny at centos.org > <mailto:johnny at centos.org>> wrote: > > On 04/18/2017 12:39 PM, PJ Welsh wrote: > > Here is something interesting... I went through the BIOS options and > > found that one R710 that *is* functioning only differed in that

Hi Could anybody explain me how to check how many L1/L2 cache my cpu have. I'm using CentOS 5.6 *cat /proc/cpuinfo |grep CPU * model name : Intel(R) Core(TM)2 Duo CPU T9300 @ 2.50GHz model name : Intel(R) Core(TM)2 Duo CPU T9300 @ 2.50GHz Diagram of a generic dual-core processor, with CPU-local level 1 caches, and a shared, on-die level 2 cache.

Hi, until recently, the hvm guest firmware for xen-ia64 was a private binary file owned and delivered by Intel. I have written an open-source implementation based on tianocore.org. The ia64 firmware is roughly speaking EFI. I have also ported tianocore to Qemu/x86. It shouldn''t be hard to port it to x86. Because the sources are big (at least 40MB) and the buildery is not easy (build

I recently post on my blog about setting up a Rails environment with RSpec in Windows, and someone left a comment saying that it doesn''t work in EdgeRails. I so I played around with it a bit and was able to confirm that none RSpec appears broken on EdgeRails. I''ll post the various error messages I received below. I''m not expecting any sort of patch or something for this

Hi. I'm going to introduce the R-package for a group of medical doctors later this week and is a little confused about there use of a test named "willcoxon-pratt" for testing if the clinical and biochemical markers has decreased significantly after the use of some drugs for a group of patients. Looking into the R-functions I would in R recommand using a matched-pairs Wilcoxon

I have a question concerning the Wilcoxon signed-rank test, and specifically, which R subroutine I should use for my particular dataset. There are three different commands in R (that I'm aware of) that calculate the Wilcoxon signed-rank test; wilcox.test, wilcox.exact, and wilcoxsign_test. When I run the three commands on the same dataset, I get different p-values. I'm hoping that