Hi Could anybody explain me how to check how many L1/L2 cache my cpu have. I'm using CentOS 5.6 *cat /proc/cpuinfo |grep CPU * model name : Intel(R) Core(TM)2 Duo CPU T9300 @ 2.50GHz model name : Intel(R) Core(TM)2 Duo CPU T9300 @ 2.50GHz Diagram of a generic dual-core processor, with CPU-local level 1 caches, and a shared, on-die level 2 cache. *http://upload.wikimedia.org/wikipedia/commons/e/ec/Dual_Core_Generic.svg* #########################>From /proc/cpuinfo we see that CPU have 6MB L2 cache, but we see it doubledand it's not true because according Intel specification we know that this CPU have shared L2 cache. *grep 'cache size' /proc/cpuinfo * cache size : 6144 KB cache size : 6144 KB ################################### Here we can see that cpu have 6MiB L2 cache and 64KiB L1 cache *dmesg |grep 'CPU: L' * CPU: L1 I cache: 32K, L1 D cache: 32K CPU: L2 cache: 6144K L2 - true L1 - not true because each CPU core have 64 KiB memory cache (Instruction and Data) ############################################ Into sys directory we can find some information about cache size but again not all information are true L2 - not true L1 - true *cat /sys/devices/system/cpu/cpu*/cache/index*/size * 32K 32K 6144K 32K 32K 6144K ##################################### getconf show information only for one core. *getconf -a |grep CACHE * LEVEL1_ICACHE_SIZE 32768 LEVEL1_DCACHE_SIZE 32768 LEVEL2_CACHE_SIZE 6291456 L1 - 64KiB - not true L2 - 6MiB - true ############################ According the most powerful tool - x86info we can presume that we have: *x86info -c * Found 2 identical CPUs Extended Family: 0 Extended Model: 1 Family: 6 Model: 23 Stepping: 6 Type: 0 (Original OEM) CPU Model (x86info's best guess): Core 2 Duo P8600 Processor name string (BIOS programmed): Intel(R) Core(TM)2 Duo CPU T9300 @ 2.50GHz Cache info L1 Instruction cache: 32KB, 8-way associative. 64 byte line size. L1 Data cache: 32KB, 8-way associative. 64 byte line size. L2 cache: 6MB, 24-way set associative, 64-byte line size. TLB info Instruction TLB: 4x 4MB page entries, or 8x 2MB pages entries, 4-way associative Instruction TLB: 4K pages, 4-way associative, 128 entries. Data TLB: 4MB pages, 4-way associative, 32 entries L1 Data TLB: 4KB pages, 4-way set associative, 16 entries L1 Data TLB: 4MB pages, 4-way set associative, 16 entries Data TLB: 4K pages, 4-way associative, 256 entries. 64 byte prefetching. Total processor threads: 2 This system has 1 dual-core processor running at an estimated 2.50GHz L1 - 128Kib - true L2 - 12 MiB - not true ########################## Output form dmidecode is useless. dmidecode -t processor L1 Cache Handle: 0x0005 L2 Cache Handle: 0x0006 L3 Cache Handle: Not Provided ################################## Is there any tool which can clearly indicate how many L1/L2 cache cpu have. If someone have any idea how to clearly designate L1/L2 cache don't hesitate share your knowledge .. ;) P.S. Sorry for my English ... Regards -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.centos.org/pipermail/centos/attachments/20110627/7278d050/attachment-0002.html>
On Mon, Jun 27, 2011 at 7:25 AM, clibup clibup <clibup at gmail.com> wrote:> Hi > > Could anybody explain me how to check how many L1/L2 cache my cpu have. > I'm using CentOS 5.6 >[...]> If someone have any idea how to clearly designate L1/L2 cache don't > hesitate share your knowledge .. >You already have the model, why don't you check the processor datasheet? Are you trying to automate some kind of data collection system? http://ark.intel.com/Product.aspx?id=33917&code=Intel%C2%AE+Core%E2%84%A22+Duo+Processor+T9300+%286M+Cache%2c+2.50+GHz%2c+800+MHz+FSB%29 http://www.intel.com/design/mobile/datashts/318914.htm -- Giovanni Tirloni -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.centos.org/pipermail/centos/attachments/20110627/28f5f834/attachment-0002.html>
On Mon, 2011-06-27 at 12:25 +0200, clibup clibup wrote:> Hi > > Could anybody explain me how to check how many L1/L2 cache my cpu > have. > I'm using CentOS 5.6On my workstation, type 4 is cpu, 7 is cache. W/no params list everything. # dmidecode --type 4,7> > <snip>Bill
Try this: http://www.open-mpi.org/software/hwloc/v1.0/ On 27/06/2011 13:25, clibup clibup wrote:> Hi > > Could anybody explain me how to check how many L1/L2 cache my cpu have. > I'm using CentOS 5.6 > > *cat /proc/cpuinfo |grep CPU * > > model name : Intel(R) Core(TM)2 Duo CPU T9300 @ 2.50GHz > > model name : Intel(R) Core(TM)2 Duo CPU T9300 @ 2.50GHz > > Diagram of a generic dual-core processor, with CPU-local level 1 > caches, and a shared, on-die level 2 cache. > > *http://upload.wikimedia.org/wikipedia/commons/e/ec/Dual_Core_Generic.svg* > > > ######################### > >From /proc/cpuinfo we see that CPU have 6MB L2 cache, but we see it > doubled and it's not true because according Intel specification we > know that this CPU have shared L2 cache. > > *grep 'cache size' /proc/cpuinfo * > > cache size : 6144 KB > > cache size : 6144 KB > > ################################### > > Here we can see that cpu have 6MiB L2 cache and 64KiB L1 cache > > *dmesg |grep 'CPU: L' * > > CPU: L1 I cache: 32K, L1 D cache: 32K > > CPU: L2 cache: 6144K > > > L2 - true > > L1 - not true because each CPU core have 64 KiB memory cache > (Instruction and Data) > > ############################################ > > Into sys directory we can find some information about cache size but > again not all information are true > > L2 - not true > > L1 - true > > *cat /sys/devices/system/cpu/cpu*/cache/index*/size * > > 32K > > 32K > > 6144K > > 32K > > 32K > > 6144K > > ##################################### > > getconf show information only for one core. > > *getconf -a |grep CACHE * > > LEVEL1_ICACHE_SIZE 32768 > > LEVEL1_DCACHE_SIZE 32768 > > LEVEL2_CACHE_SIZE 6291456 > > > L1 - 64KiB - not true > > L2 - 6MiB - true > > ############################ > > According the most powerful tool - x86info we can presume that we have: > > *x86info -c * > > > Found 2 identical CPUs > > Extended Family: 0 Extended Model: 1 Family: 6 Model: 23 Stepping: 6 > > Type: 0 (Original OEM) > > CPU Model (x86info's best guess): Core 2 Duo P8600 > > Processor name string (BIOS programmed): Intel(R) Core(TM)2 Duo CPU > T9300 @ 2.50GHz > > Cache info > > L1 Instruction cache: 32KB, 8-way associative. 64 byte line size. > > L1 Data cache: 32KB, 8-way associative. 64 byte line size. > > L2 cache: 6MB, 24-way set associative, 64-byte line size. > > TLB info > > Instruction TLB: 4x 4MB page entries, or 8x 2MB pages entries, 4-way > associative > > Instruction TLB: 4K pages, 4-way associative, 128 entries. > > Data TLB: 4MB pages, 4-way associative, 32 entries > > L1 Data TLB: 4KB pages, 4-way set associative, 16 entries > > L1 Data TLB: 4MB pages, 4-way set associative, 16 entries > > Data TLB: 4K pages, 4-way associative, 256 entries. > > 64 byte prefetching. > > Total processor threads: 2 > > This system has 1 dual-core processor running at an estimated 2.50GHz > > > L1 - 128Kib - true > > L2 - 12 MiB - not true > > ########################## > Output form dmidecode is useless. > > dmidecode -t processor > L1 Cache Handle: 0x0005 > L2 Cache Handle: 0x0006 > L3 Cache Handle: Not Provided > > ################################## > Is there any tool which can clearly indicate how many L1/L2 cache cpu > have. > > If someone have any idea how to clearly designate L1/L2 cache don't > hesitate share your knowledge .. ;) > P.S. > Sorry for my English ... > > > Regards > > > > > _______________________________________________ > CentOS mailing list > CentOS at centos.org > http://lists.centos.org/mailman/listinfo/centos-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.centos.org/pipermail/centos/attachments/20110627/e0dfd5e4/attachment-0002.html>
clibup clibup wrote:> Hi > > Could anybody explain me how to check how many L1/L2 cache my cpu have. > I'm using CentOS 5.6 > > *cat /proc/cpuinfo |grep CPU * > > model name : Intel(R) Core(TM)2 Duo CPU T9300 @ 2.50GHz > > model name : Intel(R) Core(TM)2 Duo CPU T9300 @ 2.50GHz<snip> Try dmidecode, or lshw. mark