similar to: [PATCH] vmx: fix debugctl handling

Implement tsc adjust feature IA32_TSC_ADJUST MSR is maintained separately for each logical processor. A logical processor maintains and uses the IA32_TSC_ADJUST MSR as follows: 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or subtracts) value X from the TSC, the logical processor also adds (or subtracts) value X

The first and third patches are cleaned up versions of an earlier v3 submission by Yang. 1: Nested VMX: check VMX capability before read VMX related MSRs 2: VMX: clean up capability checks 3: Nested VMX: fix IA32_VMX_CR4_FIXED1 msr emulation 4: x86: make hvm_cpuid() tolerate NULL pointers Signed-off-by: Jan Beulich <jbeulich@suse.com>

x86:x2apic: Disable x2apic on x86-32 permanently x2apic initialization on x86_32 uses vcpu pointer before it is initialized. As x2apic is unlikely to be used on x86_32, this patch disables x2apic permanently on x86_32. It also asserts the sanity of vcpu pointer before dereference to prevent further misuse. Signed-off-by: Fengzhe Zhang <fengzhe.zhang@intel.com> diff -r 02c0af2bf280

"Jan Beulich" <JBeulich at suse.com> writes: #Okay, this at least clarifies there is a (relatively big) RMRR. There is #a change to the handling of these among the ones that'll become #4.3.3 - mind giving #http://xenbits.xen.org/gitweb/?p=xen.git;a=commitdiff;h=6c63041428cc348bcb2887afabd606bc4bd5523f #a try on top of your 4.3.2 (or trying the tip of the stable-4.3 branch)? #

Currently, Xen does not support injecting an NMI to HVM guest OS. Adding this feature is necessary for those softwares which depend on NMI to function correctly, such as KDB and oprofile. The attached patch allows NMI to be injected to guest OS in NMIP capable platforms. It also enables to queue an NMI and then inject it as soon as possible. Signed-off-by: Haitao Shan

Hi, Keir, Currently, HVM guests do not have access to performance counters. So it is not possible to use performance analyzer software such as vtune in HVM guest to analyze programme performance. Other usage of performance counters , for example, the NMI watchdog, won''t function either. This patch will enable performance counters in HVM guest. Currently, only Core 2 Duo is implemented.

Changes from v1: - Define new struct hvm_trap to represent information of trap, include instruction length. - Renames hvm_inject_exception to hvm_inject_trap. Then define a couple of wrappers around that function for existing callers, so that their parameter lists actually *shrink*. This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP),

The hvm domain which is being debugged sometimes crashes with the following message: (XEN) Failed vm entry (exit reason 0x80000021) caused by invalid guest state (0). (XEN) ************* VMCS Area ************** (XEN) *** Guest State *** (XEN) CR0: actual=0x000000008005003b, shadow=0x000000008005003b, gh_mask=ffffffffffffffff ...[snip]... (XEN) DebugCtl=0000000000000000

Svm patch to add 32bit msr support (combined both 32bit with 64bit functions) and enable vlapic for 64bit. Applies cleanly to 9023. Please apply. Signed-off-by: Tom Woller <thomas.woller@amd.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

TPR shadow/threshold feature is important to speedup the boot time for Windows guest. Besides, it is a must feature for certain VMM. We map virtual APIC page address and TPR threshold from L1 VMCS, and synch it into shadow VMCS in virtual vmentry. If TPR_BELOW_THRESHOLD VM exit is triggered by L2 guest, we inject it into L1 VMM for handling. Besides, this commit fixes an issue for apic access

Hi, Keir, Jan, This patch is a bugfix pointed by Jan. Fix mask_base(actually MSI-X table base, copy name from native) to be a virtual address rather than a physical address. And remove wrong printk in pci_disable_msix. Jan, the error message you saw is wrong output from kernel''s MSI code. Really sorry for my dirty code there. Could you please review the patch and give me feedback?

Hi, Keir, This patch will add the missing MSI-X support to HVM domain. All code is added to qemu. Can I know your comments on this? Best Regards Haitao Shan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

From: Yang Zhang <yang.z.zhang@Intel.com> With virtual unrestricted guest feature, L2 guest is allowed to run with PG cleared. Also, allow PAE not set during virtual vmexit emulation. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> --- xen/arch/x86/hvm/hvm.c | 3 ++- xen/arch/x86/hvm/vmx/vvmx.c | 3 +++ 2 files changed, 5 insertions(+), 1 deletions(-) diff --git

This patch implements cpu offline feature. Best Regards Haitao Shan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Hi, Keir, This patch will move reading and writing of PCI configuration spaces from dom0 to Xen. It also changes VTD code, so that they can touch the PCI configuration spaces with proper lock. This will also benefit MSI support in Xen. Can you give some comments? Thanks! <<pci_conf_xen.patch>> Best Regards Haitao Shan _______________________________________________ Xen-devel

From: Zhang Xiantao <xiantao.zhang@intel.com> With virtual EPT support, L1 hyerpvisor can use EPT hardware for L2 guest''s memory virtualization. In this way, L2 guest''s performance can be improved sharply. According to our testing, some benchmarks can show > 5x performance gain. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Zhang Xiantao (11):

<<handle_msi_irq_storm.patch>> Hi, Keir, This patch handles MSI irq storm. Unluckily, I have observed this phenomenon again. This will happen when some kind of MSI-X capable NIC is assigned to an HVM guest. The basic idea is to mask the interrupt on receiving the second interrupt and set a timer to unmask after 1ms. Can you have a look and give some comments on that? Thanks! Best

Note, this is a cross-post from/to linux-vs mailing list Here is the setup: (monospace font required) ___ +----+ ___ / |VMR1| \ / +----+ \ / +----+ \ A(lice)------------LB-A------ |VMR2| ------LB-B------------B(ob) \ +----+ /

Hi, Keir, This patch is a bugfix for saving and restoring MSI/MSI-X across S3. Currently, Dom0''s PCI layer unmaps MSI when S3 and maps them back when resuming. However, this triggers unexpected behaviors. For example, if the drivers still holds that irq at the point of unmapping MSI, Xen will force unbind that pirq. But after resume, we have no mechanism to rebind that pirq. The device

Hi Keir, Please pull the ia64 trees: http://xenbits.xensource.com/ext/ia64/xen-unstable.hg http://xenbits.xensource.com/ext/ia64/linux-2.6.18-xen.hg This includes updates of acpi related files, save/restore update for pv_ops and bug fixes from Akio, and mini-os update from Samuel Thibault. Thanks, -- yamahata _______________________________________________ Xen-devel mailing list