similar to: [Patch] Fix some bugs in mmio decoder

Memory mapped and port I/O is currently broken under VMX when the partition is running in VM8086 mode. The reason is that the instruction decoding support uses 32-bit opcode/address decodes rather 16-bit decodes. This patch fixes that. In addition, the patch adds support for the "stos" instruction decoding because this is a frequently used way to clear MMIO areas such as the screen. As

Hi, all I want to reduce the checkpoint size of a VM by memory exclusion. I try to find out all the free pages by reference count at VMM-level, As they declared that: /* Page is on a free list: ((count_info & PGC_count_mask) == 0). */ , in struct page_info which is defined in /xen/include/asm-x86/mm.h, but unfortunately, all the pages in a idle VM accords with this condition.

Any advice about the patch cr8-acceleration-3.patch? Hi Keir, could you give some comments? Thanks! -- Dexuan -----Original Message----- From: xen-devel-bounces@lists.xensource.com [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Cui, Dexuan Sent: 2006年10月25日 11:12 To: Keir.Fraser@cl.cam.ac.uk Cc: xen-devel@lists.xensource.com Subject: [Xen-devel] [Patch][RESEND] Add hardware CR8

The Xen platform device (introduced in changeset 11161) would cause HCT''s PCI Compliance Test to generate a failure message. The patch fixes this. Thanks Dexuan Cui Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Sorry, please ignore this mail. (I attached the old patch...) -- Dexuan -----Original Message----- From: xen-devel-bounces@lists.xensource.com [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Cui, Dexuan Sent: 2006年10月25日 11:07 To: Keir.Fraser@cl.cam.ac.uk Cc: xen-devel@lists.xensource.com Subject: [Xen-devel] [Patch][RESEND] Add hardware CR8 acceleration for TPRaccessing x64

Changeset 15046:e527b4ff1948 breaks 32-bit HVM guest: when req->size is 4, "1UL << 32" returns 1 in IA32 system, so the mask becomes 0 wrongly. The attached patch fixes this by using 64-bit left-shift. Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

On platforms which supports x2APIC, the patches enable this enhancement for Xen. The x2APIC specification is available at http://www.intel.com/products/processor/manuals/ http://download.intel.com/design/processor/specupdt/318148.pdf apicid_u8_2_u32.patch: changes the ''apicid'' from u8 to u32; x2apic.patch: replaces the traditional MMIO-style interface to the MSR-style one; uses

Some operating systems access the local APIC TPR very frequently, and we handle that using software-based local APIC virtualization in Xen today. Such virtualization incurs a number of VM exits from the memory-access instructions against the APIC page in the guest. The attached patch enables the TPR shadow feature that provides APIC TPR virtualization in hardware. Our tests indicate it can

The PCI_EXP_TYPE_PCI_BRIDGE should be PCI_EXP_FLAGS_TYPE here. Also a tiny fix to the python comment. Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Eli Friedman wrote: > The reason it's the right thing to do is that the mem/imm forms of > btsw and btsl have exactly the same semantics. The Intel documentation implies that this is the case: > If the bit base operand specifies a memory location, it represents the address of the byte in memory that contains the bit base (bit 0 of the specified byte) of the bit string (see Figure

Thanks for your advice. I will re-organize the patch. Thanks -- Dexuan -----Original Message----- From: Li, Xin B Sent: 2006年10月24日 18:08 To: Petersson, Mats; Cui, Dexuan; Betak, Travis Cc: xen-devel@lists.xensource.com Subject: RE: [Xen-devel] [Patch] Add hardware CR8 acceleration for TPRaccessing >> From: xen-devel-bounces@lists.xensource.com >>

On Fri, Sep 27, 2019 at 05:37:20AM +0000, Dexuan Cui wrote: > > From: linux-hyperv-owner at vger.kernel.org > > <linux-hyperv-owner at vger.kernel.org> On Behalf Of Stefano Garzarella > > Sent: Thursday, September 26, 2019 12:48 AM > > > > Hi Dexuan, > > > > On Thu, Sep 26, 2019 at 01:11:27AM +0000, Dexuan Cui wrote: > > > ... > >

Thank you. I notice the system then jumps to F000:FFF0 to execute. But because VMX is turned on, switching to real-mode would incur problems? I don’t find any clue to turn on the vm86 mode as Readme in the tools/firmware directory puts. Best regards, Hu Jia Yi Ext: 20430 Tel: 65-67510430 -----Original Message----- From: Cui, Dexuan [mailto:dexuan.cui@intel.com] Sent: Thursday,

x64 SMP Vista HVM guest uses HPET as the main system timer, and it uses physical destination mode with broadcast to deliver the interrupts generated by HPET. In current code, timer interrupts are injected only to VCPU0 in vioapic.c, but this doesn''t satisfy x64 SMP Vista -- when it boots, it complains "a clock interrupt was not received on a secondary processor within the allocated

The attached patch adds the HPET description table to ACPI. -- Dexuan Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

In x64 SMP Vista HVM guest (vcpus=2 in the configuration file), the wall clock time is 50% slower than that in the real world. The attached patch fixes the issue. -- Dexuan Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

On Fri, Sep 27, 2019 at 05:37:20AM +0000, Dexuan Cui wrote: > > From: linux-hyperv-owner at vger.kernel.org > > <linux-hyperv-owner at vger.kernel.org> On Behalf Of Stefano Garzarella > > Sent: Thursday, September 26, 2019 12:48 AM > > > > Hi Dexuan, > > > > On Thu, Sep 26, 2019 at 01:11:27AM +0000, Dexuan Cui wrote: > > > ... > >

After changeset 18030 and 18064 were checked in, I found some issues when creating HVM domains with devices assigned: In XendDomainInfo.py, we have the call trace: the global function create() => vm.start() => _constructDomain(). In _constructDomain(), we invoke xc.test_assign_device() and when the function fails (maybe because iommu=1 is not specified in grub entry since iommu is 0 by

The datasheet is available at http://download.intel.com/design/network/datashts/82599_datasheet.pdf See 'Table 9.7. VF PCIe Configuration Space' of the datasheet, the PCI Express Capability Structure of the VF of Intel 82599 10GbE Controller looks trivial, e.g., the PCI Express Capabilities Register is 0, so the Capability Version is 0 and pt_pcie_size_init() would fail. We should not

Hi Dexuan, On Thu, Sep 26, 2019 at 01:11:27AM +0000, Dexuan Cui wrote: > Lockdep is unhappy if two locks from the same class are held. > > Fix the below warning for hyperv and virtio sockets (vmci socket code > doesn't have the issue) by using lock_sock_nested() when __vsock_release() > is called recursively: > > ============================================ >