similar to: RE: [Patch][RESEND] Add hardware CR8 acceleration for TPRaccessing

Sorry, please ignore this mail. (I attached the old patch...) -- Dexuan -----Original Message----- From: xen-devel-bounces@lists.xensource.com [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Cui, Dexuan Sent: 2006年10月25日 11:07 To: Keir.Fraser@cl.cam.ac.uk Cc: xen-devel@lists.xensource.com Subject: [Xen-devel] [Patch][RESEND] Add hardware CR8 acceleration for TPRaccessing x64

Thanks for your advice. I will re-organize the patch. Thanks -- Dexuan -----Original Message----- From: Li, Xin B Sent: 2006年10月24日 18:08 To: Petersson, Mats; Cui, Dexuan; Betak, Travis Cc: xen-devel@lists.xensource.com Subject: RE: [Xen-devel] [Patch] Add hardware CR8 acceleration for TPRaccessing >> From: xen-devel-bounces@lists.xensource.com >>

This patch adds CR8 virtualization. It''s the initial patch for booting HVM x64 Windows guest, and just let every CR8 access issues vmexit. And later we will do acceleration to it. Signed-off-by: Xiaohui Xin <xiaohui.xin@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

This patch is a small fix for CR8 acceleration on 64bit guest. For current CR8 acceleration, we do not call update_tpr_threshold() at every VMEXIT. But at some situations, we cannot inject guest interrupts in time. And at some critical time, it will bring up a blue screen to 64bit Windows guest. Try this scenario: 1) At one VMIT, tpr = TPR_THRESHOLD, but tpr < pending IRQ, and we

There is a lot of infrastructure for functionality which is used exclusively in __{save,restore}_processor_state() on the suspend/resume path. cr8 is an alias of APIC_TASKPRI, and APIC_TASKPRI is saved/restored by lapic_{suspend,resume}(). Saving and restoring cr8 independently of the rest of the Local APIC state isn't a clever thing to be doing. Delete the suspend/resume cr8 handling,

There is a lot of infrastructure for functionality which is used exclusively in __{save,restore}_processor_state() on the suspend/resume path. cr8 is an alias of APIC_TASKPRI, and APIC_TASKPRI is saved/restored by lapic_{suspend,resume}(). Saving and restoring cr8 independently of the rest of the Local APIC state isn't a clever thing to be doing. Delete the suspend/resume cr8 handling,

On 15/07/2019 19:17, Nadav Amit wrote: >> On Jul 15, 2019, at 8:16 AM, Andrew Cooper <andrew.cooper3 at citrix.com> wrote: >> >> There is a lot of infrastructure for functionality which is used >> exclusively in __{save,restore}_processor_state() on the suspend/resume >> path. >> >> cr8 is an alias of APIC_TASKPRI, and APIC_TASKPRI is saved/restored

On 15/07/2019 19:17, Nadav Amit wrote: >> On Jul 15, 2019, at 8:16 AM, Andrew Cooper <andrew.cooper3 at citrix.com> wrote: >> >> There is a lot of infrastructure for functionality which is used >> exclusively in __{save,restore}_processor_state() on the suspend/resume >> path. >> >> cr8 is an alias of APIC_TASKPRI, and APIC_TASKPRI is saved/restored

The Xen platform device (introduced in changeset 11161) would cause HCT''s PCI Compliance Test to generate a failure message. The patch fixes this. Thanks Dexuan Cui Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Changeset 15046:e527b4ff1948 breaks 32-bit HVM guest: when req->size is 4, "1UL << 32" returns 1 in IA32 system, so the mask becomes 0 wrongly. The attached patch fixes this by using 64-bit left-shift. Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

There is a lot of infrastructure for functionality which is used exclusively in __{save,restore}_processor_state() on the suspend/resume path. cr8 is an alias of APIC_TASKPRI, and APIC_TASKPRI is saved/restored independently by lapic_{suspend,resume}(). Delete the saving and restoration of cr8, which allows for the removal of both PVOPS. Signed-off-by: Andrew Cooper <andrew.cooper3 at

There is a lot of infrastructure for functionality which is used exclusively in __{save,restore}_processor_state() on the suspend/resume path. cr8 is an alias of APIC_TASKPRI, and APIC_TASKPRI is saved/restored independently by lapic_{suspend,resume}(). Delete the saving and restoration of cr8, which allows for the removal of both PVOPS. Signed-off-by: Andrew Cooper <andrew.cooper3 at

The PCI_EXP_TYPE_PCI_BRIDGE should be PCI_EXP_FLAGS_TYPE here. Also a tiny fix to the python comment. Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

On platforms which supports x2APIC, the patches enable this enhancement for Xen. The x2APIC specification is available at http://www.intel.com/products/processor/manuals/ http://download.intel.com/design/processor/specupdt/318148.pdf apicid_u8_2_u32.patch: changes the ''apicid'' from u8 to u32; x2apic.patch: replaces the traditional MMIO-style interface to the MSR-style one; uses

@@ -491,16 +512,15 @@ int pirq_guest_bind(struct vcpu *v, int int rc = 0; cpumask_t cpumask = CPU_MASK_NONE; + WARN_ON(!spin_is_locked(&v->domain->evtchn_lock)); I find this WARN_ON() is triggered harmlessly when I assign device to HVM guest. The call trace is XEN_DOMCTL_bind_pt_irq -> pt_irq_create_bind_vtd() -> pirq_guest_bind(). Should we

In x64 SMP Vista HVM guest (vcpus=2 in the configuration file), the wall clock time is 50% slower than that in the real world. The attached patch fixes the issue. -- Dexuan Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Some operating systems access the local APIC TPR very frequently, and we handle that using software-based local APIC virtualization in Xen today. Such virtualization incurs a number of VM exits from the memory-access instructions against the APIC page in the guest. The attached patch enables the TPR shadow feature that provides APIC TPR virtualization in hardware. Our tests indicate it can

The datasheet is available at http://download.intel.com/design/network/datashts/82599_datasheet.pdf See 'Table 9.7. VF PCIe Configuration Space' of the datasheet, the PCI Express Capability Structure of the VF of Intel 82599 10GbE Controller looks trivial, e.g., the PCI Express Capabilities Register is 0, so the Capability Version is 0 and pt_pcie_size_init() would fail. We should not

On Mon, Jul 15, 2019 at 6:23 AM Juergen Gross <jgross at suse.com> wrote: > > On 15.07.19 15:00, Andrew Cooper wrote: > > There is a lot of infrastructure for functionality which is used > > exclusively in __{save,restore}_processor_state() on the suspend/resume > > path. > > > > cr8 is an alias of APIC_TASKPRI, and APIC_TASKPRI is saved/restored > >

On Mon, Jul 15, 2019 at 6:23 AM Juergen Gross <jgross at suse.com> wrote: > > On 15.07.19 15:00, Andrew Cooper wrote: > > There is a lot of infrastructure for functionality which is used > > exclusively in __{save,restore}_processor_state() on the suspend/resume > > path. > > > > cr8 is an alias of APIC_TASKPRI, and APIC_TASKPRI is saved/restored > >