similar to: psad + shorewall

Displaying 20 results from an estimated 300 matches similar to: "psad + shorewall"

2003 Dec 14
0
psad + shorewall
> On Fri, 2003-09-19 at 07:10, Tom Eastep wrote: > > On Fri, 2003-09-19 at 06:59, Tom Eastep wrote: > > > On Fri, 2003-09-19 at 06:52, Petr Novák wrote: > > > > > > > Is there a way for shorewall to be comatible with psad ? > > > > > > >From the above messages, it doesn''t seem likely. > > > > > > >
2012 Aug 28
1
psad Error
Just installed psad and am testing it. This morning I awoke to an email saying: [-] You may just need to add a default logging rule to the /sbin/ip6tables ''filter'' ''INPUT'' chain on hydra. For more information, see the file "FW_HELP" in the psad sources directory or visit: http://www.cipherdyne.org/psad/docs/fwconfig.html Well I have
2003 Oct 10
0
ADMNISTRATOR PRIVILEGIES ON SAMBA 2.2.8 PDC
Hello guruz. I have big trouble. I installed SAMBA 2.2.8 from 2.2.3a. My problem is about administrator privilegies. When I log on some WIN2k workstation as root of SAMBA domain I have no admin privilegies as domain administrator(remote admin any workstation, shares modify, policy modify ...). It worked well before. I was finding solution 2 mounth but without some solution. I have no idea why
2001 Apr 19
1
boxplot()
Dear all, I am comparing: > summary(boxplot(c(1,2,3,4,5,6,7,8,50),range=1.5)) Length Class Mode stats 5 -none- numeric n 1 -none- numeric conf 2 -none- numeric out 1 -none- numeric ^^^^^ group 1 -none- numeric names 1 -none- character with: > summary(boxplot(c(1,2,3,4,5,6,7,8,50),range=0)) Length Class Mode stats 5 -none- numeric n
2002 Jan 15
1
Using R under Emacs
Dear R-help, I would like to use R 1.3.0 under emacs-20.7. with the help of ess-5.1.19 in the windows system. I downloaded the ess-5.1.19 and tried to follow instructions strictly. 1. cd to a directory where you keep emacs lisp files -------------> no question 2. Retrieve the compressed the zipped file `ESS-5.1.19.zip' from one of the FTP. -------------> no question
2015 Jan 28
2
[LLVMdev] RFC: generation of PSAD instruction
Hello, I was looking at the following test case which is very relevant in imaging applications. int sad(unsigned char *pix1, unsigned char *pix2) { int sum = 0; for( int x = 0; x < 16; x++ ) { sum += abs( pix1[x] - pix2[x] ); } return sum; } The llvm IR generated after all the IR
2015 Jan 28
5
[LLVMdev] RFC: generation of PSAD instruction
On Wed, Jan 28, 2015 at 7:50 AM, Hal Finkel <hfinkel at anl.gov> wrote: > Hi Vijender, > > Thanks for posting this, there is wide support here for improving our support for reductions of various kinds, both in flavor and robustness. I've cc'd some others who have previously discussed this. > > James has advocated in the past for an intrinsic for horizontal reductions,
2015 May 05
2
[LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics
On 4 May 2015 at 08:37, Shahid, Asghar-ahmad <Asghar-ahmad.Shahid at amd.com> wrote: > My worry is regarding the query for cost calculation for specific SAD > instructions such as ‘psad’ (X86) or ‘usad’ (ARM) in Loop Vectorizer. Hi Shahid, The vectorizer's cost model has the ability to return different costs for the same instruction based on the arguments (scalar/vector,
2003 Sep 19
0
Re: Shorewall-users Digest, Vol 10, Issue 59
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, I changed all rules to drop (Even the one in shorewall.conf) .. And PSAD works great with Shorewall here ... Although that might not be what you want. Lady Linux At 10:43 AM 9/19/2003, you wrote: >Is there a way for shorewall to be comatible with psad ? >thanks & regards >Petr Novak "No Problems Only Solutions"
2015 May 05
1
[LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics
Hi Renato, Thanks for your response. My concern was actually this. For example, take vector type V8i16 on X86 target With llvm.sad() intrinsic: VC1 (Vector Cost) = Cost associated with "PSAD" instruction. W/ llvm.absd() and llvm.hadd() VC2 = Cost associated with "absolute diff" + "horizontal add" ( ??? ) As I will be querying with getIntrinsicCost(ID) for these
2016 May 27
0
sum elements in the vector
Hi Shahid. Do you mind providing a concrete example of X86 code where an intrinsic was added (preferrable with filenames and line numbers)? I'm having difficulty tracking down the steps you provided. Any help is appreciated. On Mon, Apr 4, 2016 at 9:02 PM, Shahid, Asghar-ahmad < Asghar-ahmad.Shahid at amd.com> wrote: > Hi Rail, > > > > We had done this for generation
2016 May 28
4
sum elements in the vector
Hi Rail, Below 2 revisions might be of your interest which Detect SAD patterns and emit psadbw instructions on X86.: http://reviews.llvm.org/D14840 http://reviews.llvm.org/D14897 Intrinsics related to absdiff revisons : http://reviews.llvm.org/D10867 http://reviews.llvm.org/D11678 Hope this helps. Regards, Suyog On Sat, May 28, 2016 at 4:20 AM, Rail Shafigulin via llvm-dev < llvm-dev at
2016 May 30
0
sum elements in the vector
Suyog, Thanks for the reply. Do you know if it is possible to add a new intrinsic without actually modifying core code (ISDOpcodes.h is an example of core code)? I'd like to add this intrinsic with as little code change as possible. On Fri, May 27, 2016 at 8:59 PM, suyog sarda <sardask01 at gmail.com> wrote: > Hi Rail, > > Below 2 revisions might be of your interest which
2015 May 04
2
[LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics
Hi Asghar-Ahmed, I saw your last ping - sorry, I'm away on vacation and back on Wednesday. Generally, I'm not sure that having both absd/hadd and sad are compatible with the discussions going on in other threads, for example my thread about min and max. Given that those two intrinsics are fairly trivial to match , I don't see the need to have two different canonical forms. James On
2016 May 09
0
sum elements in the vector
I'm a little confused. Here is why. I was able to add a vector add instruction to my target without using any intrinsics and without adding any new instructions to LLVM. So here is my question: how come I managed to add a new vector instruction without adding an intrinsic and why in order to add this particular instruction (sum elements in a vector) I need to add an insrinsic? Another
2009 Jul 19
2
[LLVMdev] LLVM Hello Pass load error when using opt -load Hello.so
Thanks, Shu, I guess I haven't updated since my post went out. There are actually 2 problems: 1. mis-compilation: My LLVM-2.5 turned out to be mis-compiled using gcc-4.4.0 (surprise to me) on Debian4-32b. I tried a few different compilers, and gcc-4.0.4 (a relatively old one, again surprised me) seems to work out fine. Question: is there a good/quick/reliable way to figure out whether a
2016 Apr 04
7
sum elements in the vector
My target has an instruction that adds up all elements in the vector and stores the result in a register. I'm trying to implement it in my compiler but I'm not sure even where to start. I did look at other targets, but they don't seem to have anything like it ( I could be wrong. My experience with LLVM is limited, so if I missed it, I'd appreciate if someone could point it out ).
2016 May 12
3
sum elements in the vector
> why in order to add this particular instruction (sum elements in a vector) I need to add an insrinsic? Adding intrinsic is not the only way, it is one of the way and user WILL-NOT be required to invoke It specifically. Currently LLVM does not have any instruction to directly represent “sum of elements in a vector” and generate your particular instruction.However, you can do it without
2007 Oct 26
3
SOLUTION - Compiled Kernel and modules for XEN3.1 on PowerEdge 1950
Dear all, since it could be of interest for the list, here I post a link to compiled kernel for XEN 3.1 on a DELL PowerEdge 1950 compiled with gcc (GCC) 4.1.2 20061115 (prerelease) (Debian 4.1.1-21) on a Debian4 distribution. This is provided AS IS AND WITHOUT ANY SUPPORT AND/OR ANY RESPONSIBILITY :-) The first link (7 MB) pack all the files you should have in /boot. The second link (12 MB)
2016 May 16
0
sum elements in the vector
I'm starting to think we should directly implement horizontal operations on vector types. My suspicion is that coming up with a nice model for this would help us a lot with things like: - Idiom recognition of reduction patterns that use horizontal arithmetic - Ability to use horizontal operations in SLPVectorizer - Significantly easier cost modeling of vectorizing loops with reductions in