similar to: difference between built-in and inline assembly

Suyog, Thanks for the reply. Do you know if it is possible to add a new intrinsic without actually modifying core code (ISDOpcodes.h is an example of core code)? I'd like to add this intrinsic with as little code change as possible. On Fri, May 27, 2016 at 8:59 PM, suyog sarda <sardask01 at gmail.com> wrote: > Hi Rail, > > Below 2 revisions might be of your interest which

Hi Shahid. Do you mind providing a concrete example of X86 code where an intrinsic was added (preferrable with filenames and line numbers)? I'm having difficulty tracking down the steps you provided. Any help is appreciated. On Mon, Apr 4, 2016 at 9:02 PM, Shahid, Asghar-ahmad < Asghar-ahmad.Shahid at amd.com> wrote: > Hi Rail, > > > > We had done this for generation

I'm a little confused. Here is why. I was able to add a vector add instruction to my target without using any intrinsics and without adding any new instructions to LLVM. So here is my question: how come I managed to add a new vector instruction without adding an intrinsic and why in order to add this particular instruction (sum elements in a vector) I need to add an insrinsic? Another

Hi Chandler, Regardless of the canonical form we choose, we need code to match non-canonical associated shuffle sequences and convert them into the canonical form. We also need code to match the pattern where we extractelement on all elements and sum them into this canonical form. This code needs to exist somewhere, so we need to decide whether it exists in the frontend or the backend. Having an

> > -Most- targets use -march. > > -eric > Do you meat that in most cases -target is used along with -march instead of -target and -mcpu? -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160318/9efe3d1b/attachment.html>

On Tue, Feb 2, 2016 at 1:41 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > Let me clarify. >> >> I'm not sure I understand what you are saying. Let me post more >> information. >> >> Here is what I have defined for Escalasetflag >> >> def Escalasetflag : SDNode<"EscalaISD::SET_FLAG", SDT_EscalaSetFlag, >>

On Fri, Mar 18, 2016 at 12:49 PM, Eric Christopher <echristo at gmail.com> wrote: > > > On Wed, Mar 16, 2016 at 2:53 PM Rail Shafigulin via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> I'm confused about the clang --target, -mcpu, -march >> >> Can someone give a clear explanation on what is the difference between >> them? >>

Hi Rail, Below 2 revisions might be of your interest which Detect SAD patterns and emit psadbw instructions on X86.: http://reviews.llvm.org/D14840 http://reviews.llvm.org/D14897 Intrinsics related to absdiff revisons : http://reviews.llvm.org/D10867 http://reviews.llvm.org/D11678 Hope this helps. Regards, Suyog On Sat, May 28, 2016 at 4:20 AM, Rail Shafigulin via llvm-dev < llvm-dev at

TableGen, as a DSL language, is made up of records. Every def corresponds to a record. For example, TableGen has a class Register, and your backend will define records by def GPR8 : Register<...>. You are correct in saying that the record definition is one of the SDNode values. These correspond 1:1 to llvm::ISD::NodeType

On Fri, Jan 29, 2016 at 11:39 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > > On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> > wrote: > >> Try visualising the DAG like this. >> >> ``` >> ---- GPR:$rA >> / >> set GPR:$rd ---- add >>

I don't really know exactly why you're getting this, but it seems like you forgot the last line in your Builtins<Target>.def. Namely, the line: #undef BUILTIN On Thu, May 26, 2016 at 1:29 AM, Rail Shafigulin via llvm-dev < llvm-dev at lists.llvm.org> wrote: > I've introduced intrinsics for my target however when I compile llvm+clang > I get a a redefinition warning:

I'm starting to think we should directly implement horizontal operations on vector types. My suspicion is that coming up with a nice model for this would help us a lot with things like: - Idiom recognition of reduction patterns that use horizontal arithmetic - Ability to use horizontal operations in SLPVectorizer - Significantly easier cost modeling of vectorizing loops with reductions in

Hi Rail, We used a very simple pattern expansion (actually, not a pattern fragment). For example, for AND, ADD (horizontal sum), OR and XOR of 4 elements we use something like the following TableGen structure: class HORIZ_Op4<SDNode opc, RegisterClass regVT, ValueType rt, ValueType vt, string asmstr> : SHAVE_Instr<(outs regVT:$dst), (ins VRF128:$src),

> > No problem. At some point the machine instructions represented by a class > "MachineInstr" are transformed into a representation using class "MCInst". > This is the MC level I'm talking about. It's the representation that the > llvm-mc uses. > > Do you mind pointing out where in the code this is happening? -- Rail Shafigulin Software

> On Mar 18, 2016, at 1:47 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > > Yes this IR does not build or shuffle any vector. Try to write a function that takes 8 ints and a pointer to a <4xi32>, builds two vectors with the 8 ints, > > This might sound like a dumb question, but how does one build a vector of ints out of regular ints in IR? See:

> why in order to add this particular instruction (sum elements in a vector) I need to add an insrinsic? Adding intrinsic is not the only way, it is one of the way and user WILL-NOT be required to invoke It specifically. Currently LLVM does not have any instruction to directly represent “sum of elements in a vector” and generate your particular instruction.However, you can do it without

On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> wrote: > Try visualising the DAG like this. > > ``` > ---- GPR:$rA > / > set GPR:$rd ---- add > \ > ---- GPR:$rB > ``` > > Each instruction forms a DAG with its operands being subnodes. > >

> On Feb 1, 2016, at 16:53, Rail Shafigulin <rail at esenciatech.com> wrote: > > > > On Fri, Jan 29, 2016 at 10:03 PM, Matt Arsenault <arsenm2 at gmail.com <mailto:arsenm2 at gmail.com>> wrote: > > > On Jan 29, 2016, at 13:25, Rail Shafigulin via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > > >

GCCBuiltin just gives it a name for clang to lookup. Generally they match up with builtins that gcc also implements, but that's not a requirement. If you add a builtin with the same name to the builtin file in clang's include/clang/Basic/Builtins*.def then they will find each other. You can also just add a builtin to clang's builtin file and catch it in clang's

I'm confused about the clang --target, -mcpu, -march Can someone give a clear explanation on what is the difference between them? Originally I thought need to specify -mcpu (which I assume means CPU) and -march but then I can't figure out how --target fits into the picture. Sometimes it tells me that -march or -mcpu options is not used. I would really appreciate any help on this. --