similar to: buld_vector and shuffle_vector DAG nodes

> On Mar 18, 2016, at 1:37 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > >> I think you created a cycle, this is easy to do with SelectionDAG :) >> Basically SelecitonDAG will iterate until it does not see anything to change. So if you insert a transformation on a pattern A, that generates pattern B, while you have another transformation that matches B and

On Wed, Mar 16, 2016 at 6:38 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: > > On Mar 16, 2016, at 5:38 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > > On Wed, Mar 16, 2016 at 11:48 AM, Mehdi Amini <mehdi.amini at apple.com> > wrote: > >> Hi Rail, >> >> Two hints to begin with: >> >> 1) Makes sure you example is

TableGen, as a DSL language, is made up of records. Every def corresponds to a record. For example, TableGen has a class Register, and your backend will define records by def GPR8 : Register<...>. You are correct in saying that the record definition is one of the SDNode values. These correspond 1:1 to llvm::ISD::NodeType

On Fri, Jan 29, 2016 at 11:39 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > > On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> > wrote: > >> Try visualising the DAG like this. >> >> ``` >> ---- GPR:$rA >> / >> set GPR:$rd ---- add >>

i'm having difficulty in understanding the BUILD_VECTOR instruction and how to lower it to the an actual ISA. i looked at other targets but wasn't quite able to figure it out. would someone be able to dumb it down for me? assume i have an insert element instruction which inserts an element from a GPR to a Vector Register at a given index, i..e vset <vector register> <gpr>

On Thu, Mar 17, 2016 at 2:41 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > On Thu, Mar 17, 2016 at 10:10 AM, Rail Shafigulin <rail at esenciatech.com> > wrote: > >> On Wed, Mar 16, 2016 at 6:38 PM, Mehdi Amini <mehdi.amini at apple.com> >> wrote: >> >>> >>> On Mar 16, 2016, at 5:38 PM, Rail Shafigulin <rail at

On Wed, Mar 16, 2016 at 11:48 AM, Mehdi Amini <mehdi.amini at apple.com> wrote: > Hi Rail, > > Two hints to begin with: > > 1) Makes sure you example is vectorized on X86 for example > 2) Is your target correctly overriding the TTI (declaring the vector > register size for example) so that the vectorizer can kicks-in (see > X86TTIImpl::getRegisterBitWidth for

On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> wrote: > Try visualising the DAG like this. > > ``` > ---- GPR:$rA > / > set GPR:$rd ---- add > \ > ---- GPR:$rB > ``` > > Each instruction forms a DAG with its operands being subnodes. > >

> On Mar 18, 2016, at 12:52 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: > >> >> On Mar 18, 2016, at 12:45 PM, Rail Shafigulin <rail at esenciatech.com <mailto:rail at esenciatech.com>> wrote: >> >> On Thu, Mar 17, 2016 at 2:41 PM, Rail Shafigulin <rail at esenciatech.com <mailto:rail at esenciatech.com>> wrote: >> On Thu,

On Thu, Feb 18, 2016 at 11:22 AM, Jonathan Roelofs < jonathan at codesourcery.com> wrote: > > > On 2/18/16 12:19 PM, Rail Shafigulin via llvm-dev wrote: > >> >> >> On Thu, Feb 18, 2016 at 10:50 AM, Krzysztof Parzyszek via llvm-dev >> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> On 2/18/2016

On Thu, Feb 18, 2016 at 11:48 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 2/18/2016 1:40 PM, Rail Shafigulin wrote: > >> >> 0x3283608: i32,ch = CopyFromReg 0x3257980, 0x3283500 [ORD=1] >> [ID=9] >> 0x3283500: i32 = Register %vreg5 [ID=1] >> >> Based on the code above, CopyFromReg is a node at

My question is: How do I make clang to generate assembly with vector instruction for my target? The back story is: I've added a few vector instructions to my target and confirmed that they are used by running my code on the test below and using a following command: opt i.esencia.ll -S -march=esencia -mcpu=esencia -loop-vectorize | llc -mcpu=esencia -o i.esencia.s target datalayout =

Suyog, Thanks for the reply. Do you know if it is possible to add a new intrinsic without actually modifying core code (ISDOpcodes.h is an example of core code)? I'd like to add this intrinsic with as little code change as possible. On Fri, May 27, 2016 at 8:59 PM, suyog sarda <sardask01 at gmail.com> wrote: > Hi Rail, > > Below 2 revisions might be of your interest which

On Fri, Feb 19, 2016 at 6:10 AM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 2/18/2016 6:01 PM, Rail Shafigulin via llvm-dev wrote: > >> [(set SR:$rD, (Esenciasetflag (i32 GPR:$rA), (i32 >> immSExt16:$imm), (i32 Cond)))]> { >> > > I suspect that the "set SR:$rD" is the problem here. The Esenciasetflag

On Thu, Feb 18, 2016 at 11:34 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 2/18/2016 1:32 PM, Rail Shafigulin wrote: > >> I think this is where I'm loosing the "thread". Based on what I'm seeing >> SET_FLAG has three operands, the first of which is a CopyFromReg. So how >> come the pattern is SET_FLAG %vreg5, 3, 20 and not

Hi Shahid. Do you mind providing a concrete example of X86 code where an intrinsic was added (preferrable with filenames and line numbers)? I'm having difficulty tracking down the steps you provided. Any help is appreciated. On Mon, Apr 4, 2016 at 9:02 PM, Shahid, Asghar-ahmad < Asghar-ahmad.Shahid at amd.com> wrote: > Hi Rail, > > > > We had done this for generation

On Thu, Feb 18, 2016 at 10:50 AM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 2/18/2016 12:43 PM, Rail Shafigulin via llvm-dev wrote: > >> >> LLVM ERROR: Cannot select: 0x3284268: glue = EsenciaISD::SET_FLAG >> 0x3283608, 0x3283710, 0x3283e48 [ORD=3] [ID=11] >> 0x3283608: i32,ch = CopyFromReg 0x3257980, 0x3283500 [ORD=1] [ID=9]

On Tue, Feb 2, 2016 at 1:41 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > Let me clarify. >> >> I'm not sure I understand what you are saying. Let me post more >> information. >> >> Here is what I have defined for Escalasetflag >> >> def Escalasetflag : SDNode<"EscalaISD::SET_FLAG", SDT_EscalaSetFlag, >>

> On Mar 18, 2016, at 1:47 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > > Yes this IR does not build or shuffle any vector. Try to write a function that takes 8 ints and a pointer to a <4xi32>, builds two vectors with the 8 ints, > > This might sound like a dumb question, but how does one build a vector of ints out of regular ints in IR? See:

I'm confused about how to specify DAG patterns for a given instruction Here is an example for my target class ALU1_RR<bits<4> subOp, string asmstr, SDNode OpNode> : ALU_RR<subOp, asmstr, [(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR:$rB)))]>; def ADD : ALU1_RR<0x0, "l.add", add>; The set operation simply creates a list. The add operation