Displaying 20 results from an estimated 3000 matches similar to: "[Beginner] Understanding Tablegen language"
2020 Jul 14
2
[Beginner] Understanding Tablegen language
On 7/13/2020 21:30, Thomas Lively via llvm-dev wrote:
> Part of the problem is that ISel patterns are like their own DSL inside
> the TableGen DSL, so keywords like "ins", "outs", and "ops" aren't
> keywords at the TableGen level, but rather at the level of the ISel
> system implemented with TableGen. Copying existing patterns and reading
> the
2020 Jul 15
2
[Beginner] Understanding Tablegen language
Is there a backend to Tablegen which can dump a map of pattern-to-matched
to instruction-to-be-generated?
--help doesn't seem to indicate anything like that.
On Tue, Jul 14, 2020 at 2:13 PM Rotate Right <rightrotate5 at gmail.com> wrote:
> Thanks Matt and Thomas. I will go through them.
>
> On Tue, Jul 14, 2020, 1:35 PM Matt P. Dziubinski <matdzb at gmail.com> wrote:
2012 Jun 20
2
[LLVMdev] How to define macros in a tablegen file?
On Wed, Jun 20, 2012 at 12:26 PM, Sebastian Pop <spop at codeaurora.org> wrote:
> For reference, here is how the SPU port is using code and pattern fragments:
>
> // Holder of code fragments (you'd think this'd already be in
> // a td file somewhere... :-)
And this comment makes me think, shouldn't this class CodeFrag be
included in the same place where PatFrag is
2012 Jun 20
3
[LLVMdev] How to define macros in a tablegen file?
Possible to add a test case?
Micah
> -----Original Message-----
> From: Sebastian Pop [mailto:spop at codeaurora.org]
> Sent: Wednesday, June 20, 2012 1:40 PM
> To: Villmow, Micah
> Cc: llvmdev at cs.uiuc.edu; llvm-commits at cs.uiuc.edu
> Subject: Re: [LLVMdev] How to define macros in a tablegen file?
>
> On Wed, Jun 20, 2012 at 12:34 PM, Sebastian Pop <spop at
2011 May 09
0
[LLVMdev] [LLVMDev] Add not instruction to PTX backend
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陳韋任 wrote:
<blockquote cite="mid:20110509013918.GA13760@cs.nctu.edu.tw" type="cite">
2012 Jun 20
0
[LLVMdev] How to define macros in a tablegen file?
On Wed, Jun 20, 2012 at 12:34 PM, Sebastian Pop <spop at codeaurora.org> wrote:
> On Wed, Jun 20, 2012 at 12:26 PM, Sebastian Pop <spop at codeaurora.org> wrote:
>> For reference, here is how the SPU port is using code and pattern fragments:
>>
>> // Holder of code fragments (you'd think this'd already be in
>> // a td file somewhere... :-)
>
>
2012 Jun 20
0
[LLVMdev] How to define macros in a tablegen file?
For reference, here is how the SPU port is using code and pattern fragments:
// Holder of code fragments (you'd think this'd already be in
// a td file somewhere... :-)
class CodeFrag<dag frag> {
dag Fragment = frag;
}
class I64SETCCNegCond<PatFrag cond, CodeFrag compare>:
Pat<(cond R64C:$rA, R64C:$rB),
(XORIr32 compare.Fragment, -1)>;
def :
2012 Oct 30
0
[LLVMdev] how to define extending vector load patterns?
Hi Heikki,
> just using [(set V2I32Regs:$result, (sextloadv2i8 ADDRrr:$address))]
>
> gives me error that extloav2i8 is not defined.
I don't have a target to test this on, but looking at
include/llvm/Target/TargetSelectionDAG.td, there is an "sextloadvi8"
PatFrag, at least. I'd suggest a pattern along the lines of:
(set V2I32Regs:$result, (v2i32 (sextloadvi8
2014 Jul 03
9
[LLVMdev] MOS6502 target
Hey there!
I've started to embark on a path to try and create a backend for a 39 year old CPU with only an accumulator, two index registers, and a 256 byte stack. It does have a bank of 256 bytes before the stack that are pretty quick though.
Really, if I can get an assembler out of `llc`, that'll be success enough for me. Clang would be better, but I think that might be crazy talk.
2011 May 09
3
[LLVMdev] [LLVMDev] Add not instruction to PTX backend
Hi, Justin
> We're been writing multiclasses for each unique type of instruction. The
> current PTX_LOGIC version is for 3-operand instructions. A new multiclass
> needs to be created for 2-operand logic instructions.
I am trying to add a multiclass for 2-operand logic instructions. For
example,
multiclass PTX_LOGIC_2OP<string opcstr, SDNode opnode> {
def ripreds :
2012 Jun 20
0
[LLVMdev] [llvm-commits] How to define macros in a tablegen file?
On Wed, Jun 20, 2012 at 3:40 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> Possible to add a test case?
I am not really sure what I would check.
At first, I thought to add a testcase to test/TableGen; as this patch
does not modify tablegen, it doesn't make sense.
What kind of test should I write for this? The test should be a
tablegen file that includes
2012 Oct 30
2
[LLVMdev] how to define extending vector load patterns?
I have an operation which loads a 16 bit block of data as 2 8-bit
elements, sign extends the both parts to 32 bits and stores the result
into 64-bit vector register.
How can I define the pattern for this?
just using [(set V2I32Regs:$result, (sextloadv2i8 ADDRrr:$address))]
gives me error that extloav2i8 is not defined.
(the same principle works for scalar sextload)
So I need to define it
2012 Nov 16
2
[LLVMdev] Operand order in dag pattern matching in td files
Hi,
I have a simple question w.r.t the order of operands used in dag
pattern matching in target files. Some of them seem intuitive. But I
want to get it clarified anyway. I am using a pattern from
X86InstrFMA.td in the below example. Consider FMA3 pattern
(simplified).
let Constraints = "$src1 = $dst" in {
multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand
2012 Jun 20
3
[LLVMdev] How to define macros in a tablegen file?
Hi Micah,
On Tue, Jun 19, 2012 at 6:29 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> If the patterns only include SDNodes, then pattern fragments will work.
>
> I might be wrong, but I've yet to find a way to do it with machine instructions, which is what you seem to have here.
I found in the Cell SPU port: lib/Target/CellSPU/SPUMathInstr.td
some examples using code
2017 Feb 10
3
Enforcing in post-RA scheduling to keep (two) MachineInstrs together
Hello.
I am using the post-RA (Register Allocation) scheduler to avoid data hazards by
inserting other USEFUL instructions from the program (besides NOPs) and it breaks apart
some sequences of instructions which should remain "glued" together.
More exactly, in my [Target]ISelDAGToDAG.cpp it is possible that I replace for
example a BUILD_VECTOR with a machine SDNode called
2014 Jul 16
2
[LLVMdev] LLVM Code Generation
Hi, all !
I am doing some study about code generation in LLVM, It is a pity that
there is little introduction to it. Some paper introduces that code
generation in LLVM is based on Table Driven, and i have referred paper "*An
experiment in table driven code generation*", But it has not given me any
help. Can you give a help understanding the code generation in LLVM. Thanks
a lot.
2012 Nov 16
0
[LLVMdev] Operand order in dag pattern matching in td files
On 16 November 2012 13:41, Anitha B Gollamudi <anitha.boyapati at gmail.com> wrote:
> Hi,
>
> I have a simple question w.r.t the order of operands used in dag
> pattern matching in target files. Some of them seem intuitive. But I
> want to get it clarified anyway. I am using a pattern from
> X86InstrFMA.td in the below example. Consider FMA3 pattern
> (simplified).
>
2012 May 11
2
[LLVMdev] TableGen pattern for negated operand
I've been unable to come up with the TableGen recipe to match a
negated operand. My target asm syntax allows the following transform:
FNEG r8, r5
MUL r6, r8, r9
to
MUL r6, -r5, r9
Is there a Pattern<> syntax that would allow matching *any* opcode (or
even some subset), not just MUL, with a FNEG'd operand? I expect I can
define a PatFrag:
def fneg_su : PatFrag<(ops
2015 Jun 01
3
[LLVMdev] PIC Micropchip Backend
I am interested in developing a backend for the PIC microcontrollers.
Specifically, I plan to write for the 8-bit MCUs, but would hopefully also
support the 16 and 32 bit models (eventually). It is my understanding that
a backend for PIC16 was previously a part of the project but was dropped in
version 2.9. Is there any development on this front currently? Is there any
interest in developing this
2016 Apr 11
2
Creating an LLVM Project
Hi there,
I have a question regarding this documentation page: http://llvm.org/docs/Projects.html
IIRC LLVM has moved away from Makefile's and uses CMake only.
The question is:
Is the page outdated or is it a recommended way for creating LLVM based project?
P.S. I’m trying to create a project using CMake, though I’m seeing some issues (didn’t manage to include headers so far).
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