similar to: [llvm-exegesis]?==?utf-8?q? [RFC] Renaming Uops- classes

Hello, I've been testing llvm-exegesis on X86. Latency and inverse_throughput modes work fine but when I run uops I get an error: event not found - cannot create event uops_dispatched_port:port_0 LLVM ERROR: invalid perf event 'uops_dispatched_port:port_0' I'm running this on a i7-4790K. Am I missing something on my computer or is this not yet fully implemented? This also

On 03/15/2018 10:04 AM, Guillaume Chatelet via llvm-dev wrote: > [You can find an easier to read and more complete version of this RFC > here > <https://docs.google.com/document/d/1QidaJMJUyQdRrFKD66vE1_N55whe0coQ3h1GpFzz27M/edit?ts=5aaa84ee#>.] > > Knowing instruction scheduling properties (latency, uops) is the basis > for all scheduling work done by LLVM. > > >

Sounds like a very useful tool.  Thank you for contributing. Taking a step back and looking at the big picture, combining this with the recently contributed llvm-mca dramatically improves our scheduling and performance analysis story.  Being able to take a snippet of code on a particular machine, measure latency/throughput/ports for each instruction (this tool), and then analyze the entire

On Thu, Mar 15, 2018 at 4:41 PM, Hal Finkel via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > On 03/15/2018 10:04 AM, Guillaume Chatelet via llvm-dev wrote: > > [You can find an easier to read and more complete version of this RFC here > <https://docs.google.com/document/d/1QidaJMJUyQdRrFKD66vE1_N55whe0coQ3h1GpFzz27M/edit?ts=5aaa84ee#> > .] > > Knowing

[You can find an easier to read and more complete version of this RFC here <https://docs.google.com/document/d/1QidaJMJUyQdRrFKD66vE1_N55whe0coQ3h1GpFzz27M/edit?ts=5aaa84ee#> .] Knowing instruction scheduling properties (latency, uops) is the basis for all scheduling work done by LLVM. Unfortunately, vendors usually release only partial (and sometimes incorrect) information. Updating the

On 03/15/2018 10:49 AM, Clement Courbet wrote: > > > On Thu, Mar 15, 2018 at 4:41 PM, Hal Finkel via llvm-dev > <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > > > On 03/15/2018 10:04 AM, Guillaume Chatelet via llvm-dev wrote: >> [You can find an easier to read and more complete version of this >> RFC here >>

I am, of course, a huge fan of this effort. :) > >> >> - >> >> [??] Make the tool work for other CPUs. This mainly depends on the >> presence of performance counters. >> >> Having these requirements documented will be great. In particular, it's important to document what kind of functionality we need out of the PMU rather than any

> On May 9, 2020, at 5:12 PM, Andrea Di Biagio via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > The llvm scheduling model is quite simple and doesn't allow mca to accurately simulate the execution of individual uOPs. That limitation is sort-of acceptable if you consider how the scheduling model framework was originally designed with a different goal in mind (i.e. machine

Hi Alex, On Sun, May 10, 2020 at 4:00 PM Alex Renda <renda at csail.mit.edu> wrote: > Thanks, that’s very helpful! > > > > Also, sorry for the miscue on that bug with the 2/4 cycles — I realize now > that that’s an artifact of a change that I made to not crash when resource > groups overlap without all atomic subunits being specified: > > `echo 'fxrstor

Hey guys, I'm currently investigating broadcasts from the constant pool on Sandy Bridge. I see this comment in llvm/lib/Target/X86/X86ISelLowering.cpp: // Handle the broadcasting a single constant scalar from the constant pool // into a vector. On Sandybridge it is still better to load a constant vector // from the constant pool and not to broadcast it from a scalar. Would anyone

Hi all, In a recent IISWC paper <http://groups.csail.mit.edu/commit/papers/19/ithemal-measurement.pdf>, we've proposed BHive - a new methodology for benchmarking arbitrary basic blocks that has several advantages over the one currently used in llvm-exegesis. In particular, the new methodology: - automatically handles memory accesses in the basic block, without the need to manually

Hi everyone, Can someone help me with running llvm-exegesis tool on x86_64? I saw that I need libpfm library, but I'm still getting segmentation fault when I try to run the tool. Is there anything else I need to do (build llvm on some specific way) ? This is how I tried to run this tool: llvm-exegesis -mode=latency -opcode-name=ADD64rr Thanks, Luka -------------- next part -------------- An

Hello, I''m trying to use the VT technology on box but when I start Xen VMX is disabled by Feature Control MSR as shown in the following message: Xen version 3.0.2-3 (guill@frec.bull.fr) (gcc version 3.3.5 (Debian 1:3.3.5-13)) Wed May 31 16:07:00 CEST 2006 Latest ChangeSet: Tue May 30 18:14:05 2006 +0100 9697:18e8e613deb9 ... (XEN) Initializing CPU#0 (XEN) Detected 3391.682 MHz

Hi there I get the following error message when i try to "xm create <domid>" Error: Error creating domain: (22, ''Invalid argument'') I have included everything i can think of Thanks The DomU config is kernel = "/boot/vmlinuz-2.6.12-xenU" ramdisk = "/boot/initrd-2.6.12.6-xenU.img" memory = 128 name = "xen01" nics=1 disk = [

Hi James, thanks for the feedback. On Thu, Jul 28, 2016, at 00:22, James Aylett wrote: > This sounds great! I know sufficiently little about CJK that I won't > try to comment on that at all :) I've just opened a pull request for the CJK tokenizer: https://github.com/xapian/xapian/pull/114 > I wonder if we can arrange suitable defaults to use your > implementation with the

On Jan 4, 2018, at 11:52, Chandler Carruth via llvm-dev <llvm-dev at lists.llvm.org> wrote: > On Thu, Jan 4, 2018 at 12:31 PM Stephen Checkoway via llvm-dev <llvm-dev at lists.llvm.org> wrote: > >> As I understand it, the busy loop is to cause the speculative execution to be trapped in the loop. Was something like ud2 considered? I presume that would stop the speculative

Hi, I’m trying to work out the behavior of llvm-mca on instructions with ProcResGroups. My current understanding is: When an instruction requests a port group (e.g., HWPort015) and all of its atomic sub-resources (e.g., HWPort0,HWPort1,HWPort5), HWPort015 is marked as “reserved” and is issued in parallel with HWPort0, HWPort1, and HWPort5, blocking future instructions from reserving HWPort015

Hi, The Cyrus IMAP mail server uses Xapian as search engine. Recently, FastMail has sponsored implementation of two Xapian features: CJK word splitting and a generator for search snippets. I've been working on both features and we would be happy to get them merged into Xapian master. The CJK word tokenizer uses the word segmentation algorithms of the International Components for Unicode

Hi, I am trying to generate performance models for specific pieces of code like an omp.outlined function. Lets say I have the following code: start_collect_parallel_for_data(-1.0,-1.0,-1.0, size, “tag for this region”); #pragma omp parallel for for(auto i = 0; i < size; ++i){ // … do work } stop_collecting_parallel_for_data(); The omp region will get outlined into a new function and what I

The Patch I made for SMP dom0 is also applicable to SMP domU. The issue is same for dom0 & domu as they both are compiled from the same code. The dom0 fix I sent earlier also fixes the domU SMP issue. Thanks & Regards, Nitin ------------------------------------------------------------------------ ----------- Open Source Technology Center, Intel Corp >-----Original Message-----