similar to: Help with RISCV and QEMU in llvm testsuite lit testing

*llvm-project version:dd8a2013dc1804be1b7d9cffacad2e984300bd22* *Instructons to build LLVM+clang:* ``` cmake -G Ninja -DCMAKE_INSTALL_PREFIX=/home/llvm/workspace/llvm/llvm-project/llvm_install -DCMAKE_BUILD_TYPE="Release" -DDEFAULT_SYSROOT="/home/llvm/workspace/riscv/riscv-tc-20200220/bin/riscv32-unknown-elf"

Michael, Apologies for taking so long to get back to you. Trunk LLVM does not contain support for code generating the V extension yet. The experimental-v support you see there is only MC-layer support, where you can use the V instructions in assembly (including inline assembly). There is currently (today) no way of turning LLVM IR vector intrinsics into RISC-V V extension instructions. Hanna

I am using LLVM version 4.0.1 Running `llc -march=riscv64 math.ll` returns: #0 0x0000000000fed7d1 (llc+0xfed7d1) #1 0x0000000000fec559 (llc+0xfec559) #2 0x0000000000fec8d9 (llc+0xfec8d9) #3 0x00007f22c044e5e0 __restore_rt (/lib64/libpthread.so.0+0xf5e0) #4 0x0000000000d7faf3 (llc+0xd7faf3) #5 0x0000000000cd4b88 (llc+0xcd4b88) #6 0x0000000000cd530c (llc+0xcd530c) #7 0x00000000006858c3

Hi Everyone, I am wondering how to use RISC-V V (Vector) extension instructions in LLVM IR. In 2019 Kruppe and Espasa gave a talk [1] overviewing the Vector extension and on slide 16 [2] they show LLVM IR samples which use the vector instructions through intrinsic functions, such as: %vl = call i32 @llvm.riscv.vsetvl(i32 %n) At the time of the talk (April 2019) LLVM support for the V

I built llvm + clang from source, a github clone from today: clang version 11.0.0 (https://github.com/llvm/llvm-project.git 91aa67bf290bc7f877b1b90128284863bc31aa43) I compiled a small program: #include <stdint.h> int main() { uint8_t a = 2; uint8_t b = 5; uint8_t c = a * b; } $ clang -c -target riscv32 -march=rv32imc -g main.c Works fine. The dumped assembly seems to not know

I am using llvm-project compiling risc-v programs. llvm-project version:dd8a2013dc1804be1b7d9cffacad2e984300bd22 Instructons to build LLVM+clang: ``` cmake -G Ninja -DCMAKE_INSTALL_PREFIX=/home/llvm/workspace/llvm/llvm-project/llvm_install -DCMAKE_BUILD_TYPE="Release" -DDEFAULT_SYSROOT="/home/llvm/workspace/riscv/riscv-tc-20200220/bin/riscv32-unknown-elf"

As you will have seen from previous postings, I've been working on upstream LLVM support for the RISC-V instruction set architecture. The initial RFC <http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html> provides a good overview of my approach. Thanks to funding from a third party, I've recently been able to return to this effort as my main focus. Now feels like a good

Hi all developers, I'm changing compiler from gcc to llvm on a RISCV target now. but I found in some case the assembly code generated by llvm is much more than gcc. It cause my program's performance about 40% decrease. The flowing is a simple test code. It shows the problem. We can see than gcc prefer to use pointer to iterate the array, but llvm perfere to use index to iterate

Hi, In tablegen file inside class we have variables declared inside a class. Say in PPC there is this class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> : I<opcode, OOL, IOL, asmstr, IIC_BrB> { bits<7> BIBO; // 2 bits of BI and 5 bits of BO. bits<3> CR; bits<14> BD; How does the generator match each variable against an

Hi all, The LLVM benchmarking system produces very noisy results even on quiet machines. One of the sources of inaccuracy is the timing tool we are using. Because it is a user-space tool, the OS can context switch it and we will get an outlier result. Perf stat uses SW_TASK_CLOCK counter in kernel to measure time, therefore more accurate. It also does not get context switched. I've

Hi, I'm trying to setup the test-suite and am getting short of running it... Following the steps here: http://llvm.org/docs/lnt/quickstart.html I got as far as getting lnt installed, but when I run the "lnt runtest nt" it fails: compilers.py:81: error: unable to determine compiler version: 'clang++': 'clang version 3.2 ' Seems my string doesn't have a

Hi, people. A tiny suggestion for the system.time function. Could the returned vector have names? These could be like: c("User", "System", "Elapsed", "Sub.User", "Sub.System") That would then produce self-documenting output. -- Fran?ois Pinard http://pinard.progiciels-bpi.ca

Hello everyone, I am working to run the LLVM Nightly Testsuite on embedded arm devices. Not all of these devices can mount NFS to share a common directory tree. To mitigate this I have patched test-suite/RunSafely.sh (attached) to create a temporary directory, run the test remotely, collect the output, and cleanup after itself. The patch breaks compatibility with the current remote device model

I want to get lnt to use qemu for the execution. In that case, RHOST= is not set. But I change the Arch because I am going to run in cross mode. Then I'm setting RUNUNDER to be a script which runs qemu. In this case it builds timeit-target as a Mips which fails because this is running on x86. ~/mysandbox/bin/lnt runtest nt --sandbox ~/mysandbox --cc /local/llvmpb_a/install/bin/clang

# RFC: Atomic LL/SC loops in LLVM revisited ## Summary This proposal gives a brief overview of the challenges of lowering to LL/SC loops and details the approach I am taking for RISC-V. Beyond getting feedback on that work, my intention is to find consensus on moving other backends towards a similar approach and sharing common code where feasible. Scroll down to 'Questions' for a summary

Hi all, I'm currently working on the implementation for LLVM of the RISCV Bit Manipulation ISA extension described by Clifford Wolf in the following presentation: https://content.riscv.org/wp-content/uploads/2019/06/17.10-b_wolf.pdf and the following document: https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.90.pdf The aim is to provide the intrinsic functions to the user in

Hi LLVM developers, Thank Daniel Sanders, Aditya Nandakumar and Justin Bogner's Tutorial[1]: Head First into GlobalISel about how to port, and Aditya took BPF target as a simple instance: bool BPFCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,                                   const Value *Val, unsigned VReg) const {   assert(!Val == !VReg && "Return value

I notice that no intrinsics have been defined for the CSRRW/CSRRS/CSRRC instructions. It would be convenient to have intrinsics for these to allow CSR manipulation directly from IR code. Interestingly, this seems to be true for PowerPC (no intrinsics for mfdcr/mtdcr) and X86 (no in/out) as well. Are there plans to define standard RISCV intrinsics for this? -------------- next part

On Wednesday, 14 September 2016 15:50:20 CEST Richard W.M. Jones wrote: > --- Ah, I forgot one thing: > + else if (strstr (elf_arch, "UCB RISC-V")) { > + ret = safe_asprintf (g, "riscv%s", bits); > + goto no_strdup; > + } I guess the "riscv16", "riscv32", and "riscv64" should be documented for the

Hi Roman, > That depends. > If there's LLVM intrinsic for it, then any normal optimization pass could do it. > In cttz's case it's mainly done in LoopIdiom pass. Oh yes. Thank you! Unfortunately several of the instructions of the bit manipulation extension don't seem to have an intrinsic already in LLVM. That will require to add some passes to the middle end. >