similar to: Check sub register relations in RA

Displaying 20 results from an estimated 1000 matches similar to: "Check sub register relations in RA"

2012 Sep 10
3
[LLVMdev] Assert in LiveInterval update
Hi Jakob, I've got a good test case that I'm working on at the moment. I noticed something odd though: Is '0' a valid register unit? I'm seeing a LiveInterval with li->reg == 0 show up, which previously wasn't valid. We have a few checks around the place to disregard the '0' physreg - could these trigger on interaction with a '0' interval? That could
2012 Sep 10
0
[LLVMdev] Assert in LiveInterval update
On Sep 10, 2012, at 2:26 AM, Lang Hames <lhames at gmail.com> wrote: > I've got a good test case that I'm working on at the moment. I noticed something odd though: Is '0' a valid register unit? I'm seeing a LiveInterval with li->reg == 0 show up, which previously wasn't valid. We have a few checks around the place to disregard the '0' physreg - could
2013 May 22
2
[LLVMdev] Avoiding MCRegAliasIterator with register units
LLVM can model some quite complicated register banks now, and we even use registers to model some encoding constraints. For example, a few ARM instructions like strexd have two register operands that must be an aligned pair of consecutive GPR registers (like r0, r1). This constraint is modeled with the GPRPair register class containing R0_R1, R2_R3, ... pseudo-registers. Sometimes ISAs also
2012 Jun 01
0
[LLVMdev] Heads up: MCRegisterInfo register list functions going away
I am going to remove these functions from MCRegisterInfo: getSubRegisters() getSuperRegisters() getOverlaps() getAliasSet() They have been replaced with iterator classes, also defined in MCRegisterInfo.h: MCSubRegIterator MCSuperRegIterator MCRegAliasIterator The tree has lots of examples of how to use all three. /jakob
2016 Aug 12
4
Invoke loop vectorizer
I'm not compiling it to x86. Should loop optimizer something independent of the target? If so, should the vectorized code on IR level? On Aug 12, 2016 11:39 AM, "Daniel Berlin" <dberlin at dberlin.org> wrote: > cat > test.c > > #define SIZE 128 > > void bar(int *restrict A, int* restrict B,int K) { > > #pragma clang loop vectorize(enable)
2015 Jul 04
3
[LLVMdev] Declare multiple data type for a register class in tblegen
Oh, they have selection details in the end. Let me check that first... On Sat, Jul 4, 2015 at 4:05 PM Xiaochu Liu <xiaochu1122 at gmail.com> wrote: > Hi Matt, > > I tried debug-only=isel and have some more informations. > The steps before 'Legalized selection'( excluding it) all use v2i32 load. > At the step of 'Legalized selection', it replaced one v2i32
2016 Aug 12
2
Invoke loop vectorizer
Hi Andrey, Thanks. I found even when loop vectorizer and SLP vectorizer are enabled, my simple test still not get optimized. I also tried clang pragma in my test to force vectorization. What do you think is the problem? Test: #define SIZE 8 void bar(int *A, int* B,int K) { #pragma clang loop vectorize(enable) vectorize_width(2) unroll_count(8) for (int i = 0; i < SIZE; ++i) A[i]
2016 Aug 12
2
Invoke loop vectorizer
Hi Daniel, I increased the size of your test to be 128 but -stats still shows no loop optimized... Xiaochu On Aug 12, 2016 11:11 AM, "Daniel Berlin" <dberlin at dberlin.org> wrote: > It's not possible to know that A and B don't alias in this example. It's > almost certainly not profitable to add a runtime check given the size of > the loop. > > >
2015 Aug 27
2
preserve registers across function call
Hi Marcello, Thanks for your reply. I will try to pass down the mask! I have one more question. In my backend I return CSR_RegMask in getCallPreservedMask and return CSR_SaveList in getCalleeSavedRegs. Is that a correct setup? I dumped the regmask and found that callee saved regs are marked 1 and non-callee saved regs are 0. Thanks, Xiaochu On Wed, Aug 26, 2015 at 5:58 PM Marcello Maggioni
2016 Aug 11
2
Invoke loop vectorizer
Hi there , I use clang-cl /Qvec test.c to compile the code. But the pass LoopVectorizer is never invoked. I was wondering if this is sufficient to enable auto vectorizer? Thanks, Xiaochu -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160811/8b6cb760/attachment.html>
2013 May 24
2
[LLVMdev] Avoiding MCRegAliasIterator with register units
On 24 May 2013 17:39, Chad Rosier <mcrosier at apple.com> wrote: > One side effect of dynamically computing the aliases is that the iterator > does not guarantee that the entries are ordered or that duplicates have > been removed. > Hi Chad, Sounds like you're growing the list (thus the lookup time), rather than shrinking, as I take it was Jacob's original intention?
2015 Jul 03
2
[LLVMdev] Declare multiple data type for a register class in tblegen
Thanks. I'm gonna try tomorrow and let you know. On Thu, Jul 2, 2015 at 6:51 PM Matt Arsenault <Matthew.Arsenault at amd.com> wrote: > On 07/02/2015 06:41 PM, Xiaochu Liu wrote: > > Hi Matt, > > > > I did call addRegisterClass in TargetLowering for all the possible > > types in the register. And for typecasting instructions (i32 to i64), > > it works.
2015 Nov 24
2
[backend]two-address encoding in llvm tblgen
Hi Hal, Thanks for your reply and it is helpful! I have a quick question: When I use BuildMI to build instructions in this case, do I have to add all three of the register operands explicitly (operand 0 and 1 are the same)? Thanks, Xiaochu On Tue, Nov 24, 2015 at 3:14 PM, Hal Finkel <hfinkel at anl.gov> wrote: > ----- Original Message ----- >> From: "Xiaochu Liu via
2015 Sep 09
2
clang invokes assembler when generating obj file?
Nice! Thanks, Tom. It works. On Wed, Sep 9, 2015 at 12:30 PM Tom Stellard <tom at stellard.net> wrote: > On Wed, Sep 09, 2015 at 07:21:30PM +0000, Xiaochu Liu via llvm-dev wrote: > > Dear there, > > > > I'm trying to use clang to invoke my backend to generate obj code using > > command: > > > > clang -target x-linux-gnu global.c -c > > >
2015 Jul 22
3
[LLVMdev] build llvm on CentOS
Hi there, I was trying to build llvm on CentOS. The problem is that library on CentOS is always so old (Gcc, python). I managed to install local gcc and let cmake know. But I couldn't do so with python. I end up comment out the check in CMakeList.txt which is not good. I was wondering if anyone has experience building llvm (using cmake) using a local python? Thanks, XIaochu --------------
2016 Mar 16
2
How to prevent clang/llvm from generating floating-point instructions?
Dear there, I was trying to compile a code with only integer type variables and integer operations. Clang/llvm kept showing me llvm code with floating-point instructions (fmul, fadd, fptosi, etc.). Is there a way in Clang or llvm to stop the compiler from doing that? My experiment does not allow floating-point operations... Thanks, Xiaochu
2016 Mar 16
2
How to prevent clang/llvm from generating floating-point instructions?
Hi Tim, Thanks for your message! It turns out that the infrastructure (an outdated one) that I am working on is using gcc+dragonegg to generate llvm code: gcc -m32 -S -c -O0 -fplugin=$(DRAGONEGG_SO) -fplugin-arg-dragonegg-emit-ir $< -o $@.tmp It directly generates llvm code with fadd, etc. I'm not familiar with dragonegg plugin... Thanks, XIaochu On Wed, Mar 16, 2016 at 12:00 PM,
2015 Aug 27
2
preserve registers across function call
Dear there, I was wondering how to preserve registers (caller saved) across calls. I implemented getCalleeSavedRegs and getCallPreservedMask. But the non-callee-saved registers are still not saved by caller. I want to spill these registers in use on stack right before the call. From my understanding, the register allocator in llvm will do the spill and restoring automatically? Is there anything I
2015 Nov 24
2
[backend]two-address encoding in llvm tblgen
Dear there, I'm developing an instruction layout like: opcode | rd| ts and its semantics is: rd= rd opcode rs But when I describe it in td file like this: class R<bits<5> Op, string OpcodeStr, list<dag> Pattern> : InstV<(outs GPR:$rd), (ins GPR:$rd, GPR:$rs), !strconcat(OpcodeStr, "\t$rd, $rs"), Pattern> { bits<5> rd; bits<6> rs; let
2015 Jul 03
2
[LLVMdev] Declare multiple data type for a register class in tblegen
Hi everyone, I tried to declare multiple data type [i64, i32, v2i32] for a 64 bit register class GPR. It works OK but I have one problem that is hard to find. When I tried to map a load instruction of a v2i32 type (LOAD v2i32:$dst) to load GPR, it always generate two LOAD i32 instead of one LOAD v2i32. Any folds understand how this works? Xiaochu -------------- next part -------------- An HTML