similar to: Removing pointers from MCInstrDesc for less relocations

On 09.05.2016 05:19, Benjamin Kramer wrote: > On Mon, May 9, 2016 at 5:35 AM, Nicolai Hähnle <llvm-dev at lists.llvm.org> wrote: >> Hi everybody, >> >> I noticed today that my libLLVM-3.9svn.so has a ~1.7MB .data.rel.ro segment >> - i.e. data that needs to be touched by the dynamic linker even though it's >> ultimately read-only, and data that cannot be

Hi all, I am looking at the scheduling model of the ThunderX2. I am trying to figure out the cost of the LDADDALX instruction. The following program’s output is: name LDADDALX; class 872 microops 65535 I would have assumed that the microops are less than 20. The ThunderX2 has a detailed cost model for LSE. Could somebody tell me what I am doing wrong? Cheers, Tom #define GET_REGINFO_ENUM

Hello, I'm currently working on a rich disassembler for some ARM/Thumb environment. I wanted to keep most classes independent of the architecture, so I use MCInstrInfo and MCInstrAnalysis to find branch instructions (and other instructions writing to the program counter) and to differentiate between register definitions and uses to track all instructions the branch depends on. This works

Hello LLVM, I'd like to check TSFlags in my AsmBackend code. However AsmBackend objects don't have a reference to MCInstrInfo, which is the only way I've seen to reach TSFlags. A quickie grep shows that none of the existing targets check TSFlags in their AsmBackends. Is there any reason I shouldn't check TSFlags in AsmBackend? If not, what's the best way to go about it?

Hi all, I'm currently investigating a bug which is causing an assert to fail in lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp. See https://llvm.org/bugs/show_bug.cgi?id=28753 for repro information. To my knowledge, this problem only occurs with the SystemZ target. I'm trying to determine whether the issue is the result of an edge case in the scheduling code itself, or if it's a

> On Sep 22, 2017, at 10:34 AM, Thorsten Schütt via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi all, > > I am looking at the scheduling model of the ThunderX2. I am trying to figure out the cost of the LDADDALX instruction. The following program’s output is: > name LDADDALX; class 872 > microops 65535 > I would have assumed that the microops are less than

Could you post the .ll file with the testcase? -Krzysztof On 7/29/2016 2:38 PM, Elliot Colp via llvm-dev wrote: > Hi all, > > I'm currently investigating a bug which is causing an assert to fail in > lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp. See > https://llvm.org/bugs/show_bug.cgi?id=28753 for repro information. > > To my knowledge, this problem only occurs with

Sure, I've attached it to the bug report. Direct link is here: https://llvm.org/bugs/attachment.cgi?id=16840 - Elliot "llvm-dev" <llvm-dev-bounces at lists.llvm.org> wrote on 2016/07/29 03:46:41 PM: > From: Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> > To: llvm-dev at lists.llvm.org > Date: 2016/07/29 03:46 PM > Subject: Re: [llvm-dev]

> On Aug 24, 2015, at 4:46 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Here is the snippet that matters: > > void > InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, > SDValue Op, > unsigned IIOpNum, > const MCInstrDesc *II, >

Hi, I wonder if it is okay to add an operand that is not part of MCInstrDesc to an MI after isel? There are things going on like instruction combining, rematerialization etc, which may call MI with TI->get(opcode). If an MI would get replaced with a new instance of itself in this way, any previously added operands would get lost, as they are not part of the MCInstrDesc. RegAlloc, does

Am Mittwoch, 26. September 2012, 11:18:20 schrieb Jakob Stoklund Olesen: > Hi Christoph, > > As you noticed, MCInstrDesc doesn't distinguish between variadic uses and > defs. Since variadic instructions will always require some kind of special > handling, it doesn't seem worthwhile to make the model more detailed. I don't see what makes them so different from other

Hi Ryan, > On Aug 24, 2015, at 6:49 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Quentin, > > I apologize for the spamming here but in getVR (where VReg is assigned an RC), it calls: > > const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getSimpleValueType()); > VReg = MRI->createVirtualRegister(RC); > > My question is why is it using the

On Sep 24, 2012, at 6:39 PM, Christoph Grenz <christophg+llvm at grenz-bonn.de> wrote: > Is it possible to extend LLVM to check if 'variable_ops' is in 'ins' and/or > 'outs' in tablegen, so that MCInstrDesc could provide something like > hasVariadicDefs() and hasVariadicUses()? > > That way handling variadic instructions when disassembling would be

Quentin, This is the issue. Somewhere prior to the constrainRegClass, it's assigning the GPRBase sub class of GPR to the MOV instruction, so it can't constrain it to Base and hence has to add the COPY. Now I just need to find out why it is ignoring the TableGen defined GPRBase for the MOV MI in favor of it's sub class GPR. Thanks. On Mon, Aug 24, 2015 at 8:34 PM, Ryan Taylor

> On Aug 24, 2015, at 1:30 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > I'm trying to do something like this: > > // Dst = NewVReg's reg class > // *II = MCInstrDesc > // IIOpNum = II Operand Num > > if (TRI->getCommonSubClass(DstRC, TRI->getRegClass(II->OpInfo[IIOpNum].RegClass)) == DstRC) > MRI->setRegClass(VReg, DstRC); >

Hallo, I worked on how to handle the distinction between variadic defines and uses and my current solution is this: I introduce a new dag item in Instruction called VariadicOperandList, which by default is undefined. It keeps a marker variable_* and all operands which are placeholders for variable lists (like 'reglist' on ARM). I think it's the cleanest solution to keep them in a

> On Mar 5, 2018, at 6:14 PM, Andrew Trick via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > >> On Mar 5, 2018, at 3:38 PM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: >> >> When Ahmed and I worked on the decompiler, we first targeted MC. Going to MI was more difficult and really wouldn’t have gotten us a

Dear all, I am trying to write an AsmParser and a CodeEmitter for simple ADD instruction. Here is what I have in the TestGenInstrInfo.td: *extern const MCInstrDesc TestInsts[] = {...{ 23, 3, 1, 0, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo13, 0, nullptr }, // Inst #23 = ADD8_rr...}* I parse the instruction successfully but I am not sure what I did wrong that the Size (as you can see in

Here is the instruction in question: multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass srcAReg, RegisterClass dstReg, ValueType srcAType, ValueType dstType, Operand ImmOd, ImmLeaf imm_type> { def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, [(set dstReg:$dstD, (OpNode srcAReg:$srcA))]>; def IMM_REG :

1. MOV16Copy_IMM_REG is the instruction matched, sorry. AD is the multiclass. The IMM in my case is a global. So you can see that GPRBaseRegs, GPRBaseRegs sets the registerclass for both the src and dst operands, in this case (MOV16Copy_IMM_REG) it's the dst. 2. Yes I agree, it most likely would. Honestly, this comes across like a bug, or unintended feature. It's adding an extra COPY to