similar to: constant string as an assembly operand

Hi Tom, Thanks. It should be always ABC. What should be the iops? just (ins i8imm:$val)? what would be the placeholder for a constant string in "ins"? On Thu, Nov 5, 2015 at 4:33 PM, Tom Stellard <tom at stellard.net> wrote: > On Thu, Nov 05, 2015 at 03:20:45PM +0100, Sky Flyer via llvm-dev wrote: > > Hello all, > > > > how can one can describe a constant

Dear all, I have written an assembler which reads assembly instructions and produces the equivalent binary. I have a problem. Although I set the bit range and immediate type for an instruction like add which accepts a register and an immediate value, I can simply overflow that value and llvm/tablegen doesn't care! for example for a i8imm imm value (bits<8> val) these two produce the

On 11/6/2015 11:35 AM, Sky Flyer via llvm-dev wrote: > Guys, I stuck at this point. Could you please give me a hint how to > solve this problem without touching the LLVM backbone?! > Why LLVM doesn't let me define an instruction consisting of an operator > with no operand? Could you try it without the pattern? I.e. just this: class TestInst<string opc, string asmstr,

Hi all, I am trying to implement an instruction with no operand for example "clr" in TableGen. ----------------------------------------- e.g. *InstrInfo.td:* class TestInst<string opc, string asmstr, dag oops, dag iops, list<dag> pattern> : Instruction { ... } def int_no_operand : Intrinsic<[]>; class ALU<string opc> : TestInst<opc,

The IMM3/IMM5 come from here X86RecognizableInstr.cpp 943 TYPE("SSECC", TYPE_IMM3) 944: TYPE("AVXCC", TYPE_IMM5) On Thu, Dec 25, 2014 at 8:22 PM, Jun Koi <junkoi2004 at gmail.com> wrote: > > > On Fri, Dec 26, 2014 at 11:54 AM, Jun Koi <junkoi2004 at gmail.com> wrote: > >> hi, >> >> some instructions

Many thanks for your prompt reply. I mean, imagine you have 3 bits for condition flags in your instruction (e.g. overflow, zero, carry set, ...) for conditional executions AND there is no direct access to the Status Register, is it even possible to implement such scenario? On Fri, Jul 10, 2015 at 4:54 PM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 7/10/2015 9:32

On 7/10/2015 10:23 AM, Sky Flyer wrote: > Many thanks for your prompt reply. > > I mean, imagine you have 3 bits for condition flags in your instruction > (e.g. overflow, zero, carry set, ...) for conditional executions AND > there is no direct access to the Status Register, is it even possible to > implement such scenario? > There doesn't have to be any explicit status

Hi all, I have implemented AsmParser, CodeEmitter, and ELF object writing. AsmParser and CodeEmitter are tested and working fine, but I would like to see ELF objects build out of a parsed asm file. Is that possible? I tried this commands, but it didn't work corrctly: *llvm-mc -filetype=obj -arch=test file.s -o=a.o* and I think after an obj file is built, I should use this command but I am

Thanks a lot Tim. I am getting an error which says: "LLVM ERROR: unable to write nop sequence of 0 bytes" Is there any way that I can print out the Obj code (I mean bitstream representation of the assembly code which is going to be placed in the ELF file), before making any ELF file? Cheers, ES On Tue, Oct 13, 2015 at 3:02 PM, Tim Northover <t.p.northover at gmail.com> wrote:

For example something like STARTUP ( http://wiki.osdev.org/Linker_Scripts#STARTUP) is not accepted by the LLVM LLD. :-/ On Wed, Apr 20, 2016 at 9:08 PM, Sky Flyer <skylake007 at gmail.com> wrote: > Yeah I found it, that's nice. Thanks a milion. > Could you please tell me how can I specify my bootstrap (startup code) in > the linking process? > > > On Wed, Apr 20, 2016

What does MIOperandInfo exactly mean while defining an Operand class? e.g. here class X86MemOperand<string printMethod> : Operand<iPTR> { let PrintMethod = printMethod; let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm); } -------------- next part -------------- An HTML attachment was scrubbed... URL:

search for VAStart. Cheers, Rafael On 20 April 2016 at 14:18, Sky Flyer <skylake007 at gmail.com> wrote: > Hi Rafael, > > Thanks a lot. > For example the start entry for me is 0x11000 by default which I don't know > where it come from! I thought there should be a default thing that sets this > entry address. > > On Wed, Apr 20, 2016 at 8:05 PM, Rafael Espíndola

hi, some instructions mismatch between assembler & disassembler, like below. it seems this happens with all SSECC related instructions? thanks, Jun $ echo "cmpps xmm1, xmm2, 23" | ./Release+Asserts/bin/llvm-mc -assemble -triple=x86_64 --output-asm-variant=1 -x86-asm-syntax=intel -show-encoding .text cmpps xmm1, xmm2, 23 # encoding: [0x0f,0xc2,0xca,0x17] $

There is no default linker script. Cheers, Rafael On 20 April 2016 at 11:23, Sky Flyer via llvm-dev <llvm-dev at lists.llvm.org> wrote: > for instance, where is the internal default linker script located? How can I > change the default values, for example the star address... > > On Wed, Apr 20, 2016 at 5:17 PM, Sky Flyer <skylake007 at gmail.com> wrote: >> >>

Hi, That's what the DecoderMethod is for. Similarly ParserMatchClass for the asm parser and PrintMethod for the asm printer: def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), (ops (i32 14), (i32 zero_reg))> { let PrintMethod = "printPredicateOperand";

Hi all, is it possible in TableGen to set value to instruction bits based on the operands? In other words, parsing the instruction at the TableGen level. for instance: "add $Rd, $Rn, $imm" I want to have something like this: *Inst{8} = ($Rn == Test::A0) 1 : 0;* Is there any way to do that in TableGen? If not is there any example in the provided example codes? Cheers, ES

hi, at the moment, TEST instruction is defined with 0xf7 opcode, as demonstrated below. $ echo "0xf7 0xc0 0x00 0x00 0x00 0x22"|./Release+Asserts/bin/llvm-mc -disassemble -arch=x86 .section __TEXT,__text,regular,pure_instructions testl $570425344, %eax ## imm = 0x22000000 however, i cannot find anywhere this F7 opcode is defined in

Hi ES, From what I understand instruction parsing is divided into two parts: - Parsing an operand list (XXXAsmParser::ParseInstruction) - Turning the operand list into an actual instruction (XXXAsmParser::MatchAndEmitInstruction) The second part does the validation (e.g. how many operands, what kind, etc) while the first part only does the parsing. That's why I think in the first part

Hello James, that was also what I've planned to do but just wasn't sure. Thanks for that. On Mon, Dec 14, 2015 at 11:52 AM, James Molloy <james at jamesmolloy.co.uk> wrote: > Hi, > > You can't nest operands like that - it must be a flattened list. So: > > def *Xpred* : PredicateOperand<OtherVT, (ops *i32imm, i32imm*, i32imm), > (ops (i32 14), (i32

Interesting - the patch doesn't address this yet. It looks like we have a difference (maybe bug?) in how we handle Intel vs. AT&T inline assembly: https://godbolt.org/z/GQw9ED Suppose we're expanding an operand with an 'i' constraint, where the operand is given as, e.g. (i32* @Bar). If the inline assembly is in Intel dialect, this expands as "Bar" in AT&T syntax