similar to: [LLVMdev] forcing two instructions to be together

Reed, Couldn't you also use instruction scheduling classes and specify that the second instruction has a bypass from the first instruction? The scheduler should always schedule them together in that case. Micah > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On > Behalf Of reed kotler > Sent: Tuesday, September 17, 2013

I used the A9 schedule as an example: http://llvm.org/svn/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td The documentation could use more clarity, but this is how I was able to do it to always get two specific instructions to be scheduled together. ________________________________________ From: reed kotler [rkotler at mips.com] Sent: Tuesday, September 17, 2013 8:54 PM To: Micah Villmow

On 09/17/2013 03:52 PM, Owen Anderson wrote: > +the list again > On Sep 17, 2013, at 3:48 PM, reed kotler <rkotler at mips.com> wrote: > >> On 09/17/2013 03:46 PM, Owen Anderson wrote: >>> On Sep 17, 2013, at 3:08 PM, reed kotler <rkotler at mips.com> wrote: >>> >>>> Is there any way, except for using bundles, to force two instructions to be

On 09/17/2013 04:51 PM, Micah Villmow wrote: > Reed, > Couldn't you also use instruction scheduling classes and specify that the second instruction has a bypass from the first instruction? The scheduler should always schedule them together in that case. > > Micah > I'm not sure exactly what you mean. Can you point me to an example of that? TIA. Reed >>

That doesn't actually give you a guarantee that they won't be split up. Phases other than the scheduler may insert instructions in the middle of block (constant island pass, for example). Pseudo-instructions are the canonical answer to that problem. --Owen On Sep 17, 2013, at 11:09 PM, Micah Villmow <micah.villmow at smachines.com> wrote: > I used the A9 schedule as an

Hi all, I am really stumped on a problem for long. I could not figure out why. That is why i am here. OK, here is the problem: I tried to insert a MachineBasicBlock into a function. Here is the code snippet: // insert a machine basic block with the error_label into MF and before I // Pred is the predecessor of the block to be inserted // the new basic block is inserted right before I void

Hello, I just wrote the code like this: BuildMI(BB, NM::CALL, 1) .addExternalSymbol(("_lvksda_control_marker_" + lexical_cast<string>(bb)).c_str()); and got some unexpected string in the assembler output. The problem is that when external symbol is added to MachineInstruction, MachineOperand is created with the char*

On Fri, 15 Apr 2005, Vladimir Prus wrote: > Hello, > I just wrote the code like this: > > BuildMI(BB, NM::CALL, 1) > .addExternalSymbol(("_lvksda_control_marker_" > + lexical_cast<string>(bb)).c_str()); > > and got some unexpected string in the assembler output. The problem is > that when external

Dear All, I am working on a x86 backend machineFunction pass, where I am trying to save the hard coded address of an arbitrary machine basic block to memory in ASM. I know the assembly needed for this but am lost at how to construct the BuildMI(). Note that these machine basic blocks are not entry's to a function. but in the middle of the function. so using addGlobalAddress or

Hi, Speex-dev I've been able to get Speex to compile on SM400M(MIPSII) with problems. ------ Rebuild All started: Project: speexenc, Configuration: Debug SM400M (MIPSII) ------ Deleting intermediate and output files for project 'speexenc', configuration 'Debug|SM400M (MIPSII)' Compiling... getopt.c getopt1.c skeleton.c speexenc.c .\speexenc.c(501) : warning

Hi all, I am still stumped on the same bug. Did anyone try to insert MachineBasicBlock into a MachineFunction? Any advice will be appreciated. Thanks a lot in advance. ~Bin ---------------------------------------------------------------------------------------------------------------------------- Thanks a lot Jeff. I changed the setNumber function call to

Hello everyone, I'm working on a MachineFunctionPass that inserts a list of instructions into an Module so a later Pass can work on them. To do so I load a dummy .ll file created from a main stub, create the needed function stubs (ModulePass), insert Blocks and create instructions using BuildMI. I started with branch instructions:     const TargetMachine &TM = MF.getTarget();

Hi Evan, Evan Cheng wrote: > The patch looks great. But I do have one comment: > > +let usesCustomDAGSchedInserter = 1 in { > + let Uses = [CR0] in { > + let Uses = [R0] in > + def ATOMIC_LOAD_ADD_I32 : Pseudo< > > The "let Uses = [R0]" is not needed. The pseudo instruction will be > expanded like this later: > > + BuildMI(BB,

>> // Increment loop variable and jmp >> BuildMI(*MBB_erase, MBB_erase->end(), db, >> TII->get(X86::ADD64ri32),reg).addReg(reg).addImm(8); > > It looks like this instruction is defining virtual register "reg" the second time. Thx for your answer... Why would it define it again? I just want to use this register and add something to it... Cheers

Hi all, I’m trying to insert some add/sub and push/pop instructions in a MachineFunction pass for ARMv7-M. However, I encountered something weird. For an add, when I use BuildMI(….., TII->get(ARM::tADDi8), reg).addReg(reg).addReg(reg).addImm(imm). if reg is R0 - R7, everything is fine: I would get something like adds r1, 4 But if I use R8 - R12 as the reg in the BuildMI, I wouldn’t get

Hi, I'm having trouble using virtual register in the X86 backend. I implemented a new intrinsic and I use a custom inserter. The goal of the intrinsic is to set the content of the stack to zero at the end of each function. Here is my code: MachineBasicBlock * X86TargetLowering::EmitBURNSTACKWithCustomInserter( MachineInstr *MI, MachineBasicBlock

Hi, I'm trying to implement __builtin_setjmp / __builtin_longjmp for Sparc processors. I think I'm very close, but I can't work out how to issue BuildMI-type instructions to load the address of the recovery location (set in setjmp) into a register using the SETHI / OR combination. I can't see any equivalent code anywhere else in Sparc. I imagine this is similar if I try to make a

Hi LLVM Dev, I have an old problem that I've wanted to clean-up for some time. Our chip has gone through a number of iterations in the past few years, but with each revision there have been changes to some of the mnemonics for instructions. These are mostly very simple, for example we had a 32-bit load from memory instruction named 'LD32' in one version of the chip, but for a

Hi everyone, I am trying to expand one instruction into multiple instructions on MIPS. For example, I try to expand: sh src, imm(dst) into: (1) sb src, imm(dst) (2) srl reg0, src, 8 (3) sb reg0, (imm+1)(dst) Here, reg0 are created with createVirtualRegister. However, instr(2) will not be emitted because reg0 is useless before reg0 is defined in instr(3), it is wrong! So how to prevent the

Look for createVirtualRegister. These are examples in PPCISelLowering.cpp. Evan On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > Hi Evan, > > Evan Cheng wrote: >> The patch looks great. But I do have one comment: >> >> +let usesCustomDAGSchedInserter = 1 in { >> + let Uses = [CR0] in { >> + let Uses = [R0] in >> + def ATOMIC_LOAD_ADD_I32 :