similar to: [LLVMdev] Reflexions about a new HDL language

Displaying 20 results from an estimated 300 matches similar to: "[LLVMdev] Reflexions about a new HDL language"

2013 Aug 30
0
[LLVMdev] Some reflexions about a new HDL language
2013 Aug 30
4
[LLVMdev] Reflexions about a new HDL language
Hi, For the synthesis backend which translate to VHDL or Verilog, I don't know if I will use LLVM. It will depend on how easy it is to play with concurrent statements with LLVM. For the simulation I will use LLVM because I can anyways artificially make the compiled code sequencial. It would allow me to benefit from all the nice things from LLVM like existing optimisations. I have never
2013 Aug 30
0
[LLVMdev] Reflexions about a new HDL language
If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools). Starting from comparisons to VHDL and Verilog is like designing a new high-level programming language today that is designed to be a better high-level programming language that is
2013 Aug 30
0
[LLVMdev] Reflexions about a new HDL language
Jonas Baggett <jonasb at tranquille.ch> writes: > What are your feedbacks ? Hello Jonas, How is that related to LLVM? I see no references to LLVM on your announcement nor on your document.
2013 Sep 18
1
[LLVMdev] Reflexions about a new HDL language
Le 30. 08. 13 11:59, David Chisnall a écrit : > If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools). That's a good idea before I go too far , and I think that MyHDL worths a look too. For Symbolics Processor Designer, I tried
2013 Aug 30
0
[LLVMdev] Some reflexions about a new HDL language
Please don't respond to this thread, since the first message was in HTML only. Response rather to the thread "Reflexions about a new HDL language".
2011 Oct 02
7
[LLVMdev] LLVM and VHDL simulation
Hi, I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process. To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis is not a list of assembly instructions but a description of a circuit with logical gates. This
2008 Jul 03
3
Active-HDL
Hey! I was wondering if active-HDL (VHDL simulator) will work with WINE 1.0? active-HDL (i regret to say) is only for windows.... :( Thanks :)
2007 Aug 28
1
HDL F10 brazilian doorbell device + TDM2400
Hi, I'm trying to connect an HDL F10 device for a friend living in Brazil to the TDM2400 on his Asterisk server. That device should behave like a normal doorbell and it is if connected to an analog PBX. I connected to the TDM2400 and everything works fine except for one thing: when the called party hangs up his phone, the F10 HDL device does not hang up. I'm not brazilian and not
2013 Jan 03
20
[Bug 58984] New: DRM NOUVEAU: probe of 0001:01:00.0 failed with error -12
https://bugs.freedesktop.org/show_bug.cgi?id=58984 Priority: medium Bug ID: 58984 Assignee: nouveau at lists.freedesktop.org Summary: DRM NOUVEAU: probe of 0001:01:00.0 failed with error -12 QA Contact: xorg-team at lists.x.org Severity: normal Classification: Unclassified OS: Linux (All)
2009 Aug 20
8
mysql sip realtime
Hi I have some question about mysql realtime. 1) Anyone know exactly if there is a specific order to declare sip table column for realtime ? In which file can I find that order ? 2) In my extconfig.conf, [settings] are : sipusers => mysql,general,siptable sippeers => mysql,general,siptable so means that I use realtime dynamic exactly ? Is it normal if some parameters from sip.conf still
2011 Oct 06
0
[LLVMdev] LLVM and VHDL simulation
On Sun, Oct 2, 2011 at 4:24 PM, Baggett Jonas <Jonas.Baggett at hefr.ch> wrote: > Hi, > > I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process. > To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis
2015 Feb 25
2
[PATCH 2/2] nouveau: Do not add most bo's to the global bo list.
On Wed, Feb 25, 2015 at 10:35 AM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > pthread_mutex_lock had *better* imply a compiler barrier across which > code can't be moved... which is very different from the printf case > where it might have done it due to register pressure or who knows > what. > In the dummy function, register pressure was certainly not an issue, but
2011 Nov 14
1
Older Nvidia hardware driver state
Hi all! I read that the older Nvidia hardware (maybe < GF8) is in a different driver and no longer maintained. Is that the case? I have a GeForce 4000 MX that I'm trying to get to work on debian/sparc64, which I admit is a bit of longshot, but I was wondering how much effort it would take to even get the driver to build, and then to function. I'm very proficient in C but don't have
2008 May 14
0
NFS subdirectory on client is out of sync
Today a user asked me whether a file on one host can be different on another host. I was busy composing an answer to tell that the /home space on all clients are mounted using NFS from the file server. Any host will therefor see the same file. The user pointed me to his file and I copied this file from the client and compared this with the file on the file server. To my surprise it turned out
2011 Oct 07
0
[LLVMdev] Vlang - TR : LLVM and VHDL simulation
Hi Jonas, >Thanks for your answers. > >In one year, I am going to have something like a semester project. >The idea I have for this project would be to create (for simulation only) a VHDL front-end to LLVM, compile some VHDL code with the newly created compilator and also with a commercial compilator and simulator and compare the performance of both simulations. I won't have the
2008 Jan 25
0
Re: how hard it would be to implement a flac-decoder in VHDL
Quoting flac-dev-request@xiph.org: > Send Flac-dev mailing list submissions to > flac-dev@xiph.org > > To subscribe or unsubscribe via the World Wide Web, visit > http://lists.xiph.org/mailman/listinfo/flac-dev > or, via email, send a message with subject or body 'help' to > flac-dev-request@xiph.org > > You can reach the person managing the list at >
2011 Oct 06
0
[LLVMdev] TR : LLVM and VHDL simulation
Thanks for your answers. In one year, I am going to have something like a semester project. The idea I have for this project would be to create (for simulation only) a VHDL front-end to LLVM, compile some VHDL code with the newly created compilator and also with a commercial compilator and simulator and compare the performance of both simulations. I won't have the time to do a full VHDL
2014 Sep 02
2
[LLVMdev] Python to VHDL using LLVM; was "Re: LLVMdev Digest, Vol 123, Issue 3"
The only VHDL to LLVM project that I know of is nvc. [0] I haven't tried it personally and from a cursory look through the source it seems like there is a LLVM backend and a "native" backend (not sure what that means). If you're really crazy you might want to see if you could massage GHDL [1] (VHDL GCC frontend) + DragonEgg [2] (LLVM backend for GCC) to get you LLVM IR. I'm
2011 Oct 06
0
[LLVMdev] MIPS 32bit code generation
A simulator should be expecting the machine opcodes not macros. LD shouldn't care at all as long as the object format plays well. I would think it would be better to fix the simulator. Jack ________________________________________ From: llvmdev-bounces at cs.uiuc.edu [llvmdev-bounces at cs.uiuc.edu] on behalf of llvmdev-request at cs.uiuc.edu [llvmdev-request at cs.uiuc.edu] Sent: Thursday,