similar to: [LLVMdev] Metadata in the backend

Hello, I'm trying to extract the value out of my MDNode, but for some reason I can't. For example, if one part of the code gets an MDNode that was created as follows: Metadata* vals[2] = { ValueAsMetadata::get(&F), ValueAsMetadata::get(ConstantInt::get(context, 135)) }; MDNode* mdnode = MDNode::get(context, vals); Is it possible to extract the value of the constant int

Is it just an optimization pass? Maybe I can cancel it somehow with a flag or by doing some code editing? Can you point me to which passes may do that? I'm working on editing a backend that can't work with anything larger than 32 bits. Does the legalize stage work on IR code? Maybe i can use that? On Jan 29, 2015 5:41 AM, Ruiling Song <ruiling.song83 at gmail.com> wrote: LLVM

Generally legalize at IR level is not a good idea. But if you need legalization on IR code, you can check PNaCl project. https://chromium.googlesource.com/native_client/pnacl-llvm/ The pass is located at: lib/Transforms/NaCl/ExpandLargeIntegers.cpp You need make some change, as the pass split large integer into 64bit integers. 2015-01-29 16:06 GMT+08:00 Alon Shaltiel (ashaltie) <ashaltie at

Most likely candidate for sure. Not a helpful error message though :( -eric On Wed, Nov 14, 2012 at 8:17 AM, Craig Topper <craig.topper at gmail.com>wrote: > I believe it's failing on 64-bit because that's a 32-bit indirect jump. > 64-bit needs jmp *%rdx. > > > On Wednesday, November 14, 2012, Shaltiel, Alon wrote: > >> ** ** >> >> ** **

From: Shaltiel, Alon Sent: Wednesday, November 14, 2012 11:39 AM To: 'llvmdev at cs.uiuc.edu' Subject: Clang error - CPU feature not currently enabled Hello, I'm trying to use clang to compile a file on Mac OS (x86_64) and get the following error. <inline asm>:4:2: error: instruction requires a CPU feature not currently enabled jmp *%edx ^ fatal error: error in

I believe it's failing on 64-bit because that's a 32-bit indirect jump. 64-bit needs jmp *%rdx. On Wednesday, November 14, 2012, Shaltiel, Alon wrote: > ** ** > > ** ** > > *From:* Shaltiel, Alon > *Sent:* Wednesday, November 14, 2012 11:39 AM > *To:* 'llvmdev at cs.uiuc.edu <javascript:_e({}, 'cvml', > 'llvmdev at cs.uiuc.edu');>'

Yep. That diagnostic is terrible. As of r167937 we get: error: instruction requires: 32-bit mode jmp *%edx ^ -Jim On Nov 14, 2012, at 8:41 AM, Eric Christopher <echristo at gmail.com> wrote: > Most likely candidate for sure. Not a helpful error message though :( > > -eric > > > On Wed, Nov 14, 2012 at 8:17 AM, Craig Topper <craig.topper at gmail.com> wrote:

Hi, As I understand it, the issue is that (at least in principle) the information in any of the C/C++ system headers can be different between different architectures (and even major versions of the standard library on a given architecture). As such, clang/clang++ attempts to find the system header file for the target architecture rather than the host, and for general code there's no way to

Hello, I'm trying to use clang to compile a file in an x86 machine (running i386 GNU/Linux) to ARM. In the end, all I want is for the bit code (I use -emit-llvm) getArch() result to be Triple::ARM. I tried to use "-target arm" but I get a "fatal error: 'bits/predefs.h' file not found". Is there any easy way to make the target architecture "ARM" without

Hello, I'm trying to use clang to compile a file on Mac OS (x86_64) and get the following error. <inline asm>:4:2: error: instruction requires a CPU feature not currently enabled jmp *%edx ^ fatal error: error in backend: Error parsing inline asm This file does compile on an Ubuntu 32bit machine I checked on google and didn't find anything helpful about it. Does

Hello, I'm trying to apply the reg2mem pass on my bc file, but it somehow adds an instruction before a landingpad instruction and so I get a broken module error: The unwind destination does not have a landingpad instruction! %41 = invoke %class.x* @_ZN10xC2Ev(%class.x* %.reload19) to label %.noexc unwind label %88

Hi, For the following case, $ cat bad1.ll target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" define internal void @test(i32 %v) { entry: %tmp = alloca i32, align 4 store i32 %v, i32* %tmp, align 4 %0 = bitcast i32* %tmp to <2 x i8>* %1 = load <2 x i8>* %0, align 4 ret void } I

Andrew Lenharth wrote: > On Fri, 2005-03-18 at 05:04 +0900, Duraid Madina wrote: >> - No varargs > > What are your issues here? Or are they simply at the "not implemented > so I don't know" stage? The two bugs I mentioned (no varargs, no alloca) are pretty much two sides of the same coin: I'm ignoring the IA64 stack frame layout (for no good reason), so

On Fri, 18 Mar 2005, Duraid Madina wrote: >>> - No instruction scheduling/bundling of any sort >> >> So this one needs to be coordinated. Next week, I might see about >> adding MachineInstruction support to the SelectionDAG so you can load up >> a DAG post-ISel and then spit it back out scheduled. > > That would be much appreciated, particularly if it

Hi As i didn't get any respons I am reformulating my question in the hope to make myself more clear. Has anyone an idea how to use metadata present in the llvm ir to guide the if-conversion in llc (as metadata get's dropped during SelectionDAG) ? -Michael 2013/4/13 Michael D'Hont <michael.dhont at ugent.be> > The project I am working on is to use the llvm toolchain for

On Fri, 2005-03-18 at 05:04 +0900, Duraid Madina wrote: > Hi everyone, > > I've just checked in an IA64 backend to LLVM! Be warned, it's pretty > rough right now. Here are some of the known defects: > > - No varargs What are your issues here? Or are they simply at the "not implemented so I don't know" stage? Namely, I am working on some varargs

The project I am working on is to use the llvm toolchain for embedded CGRA processors . This however poses some restrictions on the block formation, because modulo scheduling is applied in a later stage. For this reason the idea was to create custom pragma's to generate metadata and attach it to de branches of loops we wanted to map on a cgra module. It is a lot similar to the loop parallell

Hi all, I need to add thread-switching support to Unladen Swallow's JIT, and LLVM's safe point support looks like a good way to get code into all the right places. However, http://llvm.org/docs/GarbageCollection.html#collector-algos points out that there's no way to emit code at safe points yet, and there are no loop safe points at all. So I'll be trying to implement them. Is

Hi everyone, I've just checked in an IA64 backend to LLVM! Be warned, it's pretty rough right now. Here are some of the known defects: - No varargs - No alloca - No instruction scheduling/bundling of any sort ...or in other words, it breaks often and when it does work, it's a dog. On the plus side, it _does_ have a tasty new pattern instruction selector. :) Beyond fixing the

On Monday 19 January 2009 16:42, Dan Gohman wrote: > >> Perhaps you want to do this after register allocation is done. Dan is > >> developing the post-allocation scheduler. You can try it out. > > > > Interesting. Can it already be found SVN? I will search the mail > > archive > > later, if not. > > Yes, it is in SVN. It's new, and so far