similar to: [LLVMdev] Folding nodes with more than one use during ISel

On Thu, Jan 14, 2016 at 6:05 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 1/13/2016 4:47 PM, Phil Tomson wrote: > >> >> First off, I got this idea from the LLVM Cookbook chapter 8: Writing an >> LLVM Backend: Lowering to multiple instructions. (now I'm having my >> doubts as to whether this is the right approach) >> > >

On Monday 22 February 2010 13:26:54 David Greene wrote: > On Monday 22 February 2010 13:06:39 Chris Lattner wrote: > > > Just wanted to clarify in case someone was wondering about this. > > > > I'm currently working in this area. What pattern is causing the cycle? > > Can I get a testcase? > > I'll see if I can generate one and file a PR. Ah,

Hello, David > Ah, isLegalToFold saves us on trunk.  But we lose folding due to prefetching, > which is unfortunate. > > I am seeing the error with 2.5 (yes, we are upgrading!). > > I guess I'll have to backport some of the isLogalToFold logic. There was x86-only code at pre-2.6 times which was later moved into generic hook named "isLegalAndProfitableToFold". You

Hi, It seems like CodeEmitterGen gets confused when we use named suboperands. sample code: def memsrc : Operand<i16> { let PrintMethod = "printSrcMemOperand"; let MIOperandInfo = (ops GR16:$ra, i16imm:$imm_i16); let ParserMatchClass = memAsmOperand; } def LOAD16m : Inst32rri<0x0, (outs GR16:$rb), (ins memsrc:$src2), "ldi16 {$rb,

Hi Eli, Thanks for the response I have one question inline. Regards, Ben [...] > The main problem that I have hit is regarding the use of CL register in the > shift instructions. The problem is that ATT syntax states that it should be > referenced as "%cl" while Intel says just "cl" but these references occur in > X86InstInfo.td and this means that it is shared

My system is a dual Xeon E5540 (Nehalem) HP Proliant DL380G6. When switching between Xen 4.0.2-rc1-pre and Xen 4.1-unstable I noticed that the NUMA info as shown by the Xen ''u'' debug-key is different. More specifically, the CPU to node mapping is alternating for 4.0.2 and grouped sequentially for 4.1. This difference affects the allocation (wrt node/socket) of pinned VCPUs to the

Hi everyone, I am puzzled by several instruction defines in MSP430. 1 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src), "mov.w\t{$src, $dst}", [ ]>; Because it's an empty dag pattern[ ], by what does instuction selector select intruction 'MOV16rr'? 2 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects =

Package: xen-hypervisor-3.4-amd64 Version: 3.4.2-2 Severity: critical Justification: breaks the whole system -- Dump: (XEN) Xen version 3.4 (Debian 3.4.2-29 (XEN) Command line: com1=115200,8n1 console=com1,vga loglvl=all guest_loglvl=all noreboot (XEN) Video information: (XEN) VGA is text mode 80x25, font 8x16 (XEN) VBE/DDC methods: none; EDID transfer time: 1 seconds (XEN) EDID info not

Package: xen-hypervisor-3.4-amd64 Version: 3.4.2-2 Severity: critical Justification: breaks the whole system -- Dump: (XEN) Xen version 3.4 (Debian 3.4.2-29 (XEN) Command line: com1=115200,8n1 console=com1,vga loglvl=all guest_loglvl=all noreboot (XEN) Video information: (XEN) VGA is text mode 80x25, font 8x16

I''ve a problem with managing power consumption on Intel Nehalem CPU. I''ve installed Xen 3.4 on our Dell PowerEdge T610 system on a Ubuntu 9.04 distribution. I recompiled the kernel 2.6.30rc5. Now I can see the c-states of the CPUs but no access to P-states information and the frequency scaling does not work. By the way, if I run the kernel 2.6.28.13 which is the last one

Hi, 1. This instruction is not selected automatically by the instruction selector. The instruction combine / select stages insert registercopies, and they are expanded later on by the copyRegToReg() function provided by the MSP430InstrInfo to this MOV16rr. 2. ReMaterializable means there is no need to find a way to preserve the value in a register : the instruction can be just be reissued

Hi, While working some more on the backend, I've added callee register saving and have come across something odd (I assume its because i've not implemented something), this is with optimisations which makes it even more odd : MOV.L [R7+ 12], R1 ; 4-byte Folded Spill MOV.L [R7+ 8], R2 ; 4-byte Folded Spill ADD.L R0,R0 + R1 ADD.L

Hi, i''m not sure if i understood the new acpi xen cpufreq driver - here''s the output when loading xen_acpi_processor module in linux 3.4: dom0 dmesg: [ 32.728151] xen-acpi-processor: (CX): Hypervisor error (-22) for ACPI CPU8 [ 32.728156] xen-acpi-processor: (CX): Hypervisor error (-22) for ACPI CPU9 [ 32.728160] xen-acpi-processor: (CX): Hypervisor error (-22) for

Hi there We have a pair of servers running FreeBSD 9.1-RC3 that act as transparent layer 7 loadbalancer (relayd) and pop/imap proxy (dovecot). Only one of them is active at a given time, it's a failover setup. From time to time the active one gets in a state in which the 'thread taskq' thread uses up 100% of one cpu on its own, like here: ---- PID USERNAME PRI NICE SIZE

On Feb 22, 2010, at 8:41 AM, David Greene wrote: > On Monday 22 February 2010 10:31:24 David Greene wrote: > >> The fundamental issue is that the DAG originally looked like this: >> >> MIN >> LOAD B >> PREFETCH >> Chain from LOAD A >> LOAD A > > Actually, it looked like this: > > MIN > LOAD B > Chain from PREFETCH

On Monday 22 February 2010 13:06:39 Chris Lattner wrote: > > Just wanted to clarify in case someone was wondering about this. > > I'm currently working in this area. What pattern is causing the cycle? > Can I get a testcase? I'll see if I can generate one and file a PR. -Dave

On Wed, Jan 13, 2016 at 2:08 PM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 1/13/2016 2:26 PM, Phil Tomson via llvm-dev wrote: > >> I've got this PseudoOp defined: >> >> def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>]>; >> def XSTGRELADDR :

Hello > Finally, I don't know how to describe following instructions in > MCoreInstrInfo.td, because of its variable ins/outs. Or what other files > should I use to finish this description? Do you need the isel support for them? If yes, then you should custom isel them. iirc ARM and SystemZ backends have similar instructions, while only the first one supports full isel for them. In

I''ve got a new system with Dual Quad Core Intel E5520 processors and Intel 82576 NICs built on the motherboard (this is a Supermicro Nehalem based blade). I''m running Xen 3.4.2, but I''ve also tried 3.4.1 and had the same problem. Dom0''s network works flawlessly, but the DomU systems all have network issues. Whenever they transmit large packets, it is as if

On Mon, Jun 15, 2009 at 5:49 PM, Gaster, Benedict<Benedict.Gaster at amd.com> wrote: > I would like to use the LLVM x86 code generator to emit Intel syntax that is > compatible with Microsoft’s MASM 9.x. Taking the TOT LLVM, from last week, I > have found a number of changes that are required to make this work, most of > which are straight forward but a couple I wanted to check